DM54S257 Datasheet, PDF (1/8 Pages) National Semiconductor (TI) – TRI-STATE QUAD 1 OF 2 DATA SELECTORS / MULTIPLEXERS

June 1989
DM54S257 DM74S257 DM54S258 DM74S258
TRI-STATE Quad 1 of 2 Data Selectors Multiplexers
General Description
These Schottky-clamped high-performance multiplexers
feature TRI-STATE outputs that can interface directly with
data lines of bus-organized systems With all but one of the
common outputs disabled (at a high impedance state) the
low impedance of the single enabled output will drive the
bus line to a high or low logic level To minimize the possibil-
ity that two outputs will attempt to take a common bus to
opposite logic levels the output enable circuitry is designed
such that the output disable times are shorter than the out-
put enable times
This TRI-STATE output feature means that n-bit (paralleled)
data selectors with up to 258 sources can be implemented
for data buses It also permits the use of standard TTL reg-
isters for data retention throughout the system
Features
Y _{TRI-STATE versions S157 S158 with same pin-outs}
Y _{Schottky-clamped for significant improvement in A-C}
performance
Y _{Provides bus interface from multiple sources in high-}
performance systems
Y _{Average propagation delay from data input}
S257 4 8 ns
S258 4 ns
Y _{Typical power dissipation}
S257 320 mW
S258 280 mW
Connection Diagrams
Dual-In-Line Package
Dual-In-Line Package
TL F 6482 – 1
Order Number DM54S257J DM54S258J DM54S257W DM74S257N or DM74S258N
See NS Package Number J16A N16E or W16A
TL F 6482 – 2
Function Table
Inputs
Output Y
Output
Control
Select
A
B
S257
S258
H
X
XX
Z
Z
L
L
LX
L
H
L
L
HX
H
L
L
H
XL
L
H
L
H
XH
H
L
H e High Level L e Low Level X e Don’t Care
Z e High Impedance (off)
TRI-STATE is a registered trademark of National Semiconductor Corporation
C1995 National Semiconductor Corporation TL F 6482
RRD-B30M105 Printed in U S A