DM54LS377 Datasheet, PDF (1/6 Pages) National Semiconductor (TI) – Octal D Flip-Flop with Common Enable and Clock

May 1992
DM54LS377 DM74LS377
Octal D Flip-Flop with Common Enable and Clock
General Description
The ’LS377 is an 8-bit register built using advanced low
power Schottky technology This register consists of eight
D-type flip-flops with a buffered common clock and a buff-
ered common input enable The device is packaged in the
space-saving (0 3 inch row spacing) 20-pin package
Features
Y _{8-bit high speed parallel registers}
Y _{Positive edge-triggered D-type flip-flops}
Y _{Fully buffered common clock and enable inputs}
Connection Diagram
Dual-In-Line Package
TL F 9831 – 1
Order Number DM54LS377E DM54LS377J
DM54LS377W DM74LS377WM or DM74LS377N
See NS Package Number
E20A J20A M20B N20A or W20A
Pin Names
E
D0 – D7
CP
Q0 – Q7
Description
Enable Input (Active LOW)
Data Inputs
Clock Pulse Input (Active Rising Edge)
Flip-Flop Outputs
C1995 National Semiconductor Corporation TL F 9831
RRD-B30M115 Printed in U S A