DM54LS323 Datasheet, PDF (1/8 Pages) National Semiconductor (TI) – 8-Bit Universal Shift/Storage Register with Synchronous Reset and Common I/O Pins

April 1992
DM54LS323 DM74LS323
8-Bit Universal Shift Storage Register
with Synchronous Reset and Common I O Pins
General Description
The ’LS323 is an 8-bit universal shift storage register with
TRI-STATE outputs Its function is similar to the ’LS299
with the exception of Synchronous Reset Parallel load in-
puts and flip-flop outputs are multiplexed to minimize pin
count Separate inputs and outputs are provided for flip-
flops Q0 and Q7 to allow easy cascading Four operation
modes are possible hold (store) shift left shift right and
parallel load All modes are activated on the LOW-to-HIGH
transition of the Clock
Features
Y _{Common I O for reduced pin count}
Y _{Four operation modes shift left shift right parallel load}
and store
Y _{Separate continuous inputs and outputs from Q0 and}
Q7 allow easy cascading
Y _{Fully synchronous reset}
Y _{TRI-STATE outputs for bus oriented applications}
Connection Diagram
Dual-In-Line Package
TL F 9829 – 1
Order Number DM54LS323J DM54LS323W DM74LS323WM or DM74LS323N
See NS Package Number J20A M20B N20A or W20A
Pin Names
Description
CP
D_S0
D_S7
S0 S1
SR
OE1 OE2
I O0–I O7
Q0 Q7
Clock Pulse Input (Active Rising Edge)
Serial Data Input for Right Shift
Serial Data Input for Left Shift
Mode Select Inputs
Synchronous Reset Input (Active LOW)
TRI-STATE Output Enable Inputs (Active LOW)
Parallel Data Inputs or TRI-STATE
Parallel Outputs
Serial Outputs
TRI-STATE is a registered trademark of National Semiconductor Corporation
C1995 National Semiconductor Corporation TL F 9829
RRD-B30M115 Printed in U S A