DM54LS165 Datasheet, PDF (1/6 Pages) National Semiconductor (TI) – 8-Bit Parallel In/Serial Output Shift Registers

May 1992
DM54LS165 DM74LS165 8-Bit Parallel
In Serial Output Shift Registers
General Description
This device is an 8-bit serial shift register which shifts data in
the direction of Q_A toward Q_H when clocked Parallel-in ac-
cess is made available by eight individual direct data inputs
which are enabled by a low level at the shift load input
These registers also feature gated clock inputs and comple-
mentary outputs from the eighth bit
Clocking is accomplished through a 2-input NOR gate per-
mitting one input to be used as a clock-inhibit function Hold-
ing either of the clock inputs high inhibits clocking and hold-
ing either clock input low with the load input high enables
the other clock input The clock-inhibit input should be
changed to the high level only while the clock input is high
Parallel loading is inhibited as long as the load input is high
Data at the parallel inputs are loaded directly into the regis-
ter on a high-to-low transition of the shift load input regard-
less of the logic levels on the clock clock inhibit or serial
inputs
Features
Y _{Complementary outputs}
Y _{Direct overriding (data) inputs}
Y _{Gated clock inputs}
Y _{Parallel-to-serial data conversion}
Y _{Typical frequency 35 MHz}
Y _{Typical power dissipation 105 mW}
Connection Diagram
Dual-In-Line Package
TL F 6399 – 1
Order Number DM54LS165J DM54LS165W DM74LS165WM or DM74LS165N
See NS Package Number J16A M16B N16E or W16A
Function Table
Shift
Load
Clock
Inhibit
Inputs
Clock
Serial
Parallel
AH
Internal
Outputs
Q_A
Q_B
L
X
X
X
ah
a
b
H
L
L
X
H
L
u
H
H
L
u
L
H
H
X
X
X
Q_A0
Q_B0
X
H
Q_An
X
L
Q_An
X
Q_A0
Q_B0
H e High Level (steady state) L e Low Level (steady state)
X e Don’t Care (any input including transitions)
u e Transition from low-to-high level
a h e The level of steady-state input at inputs A through H respectively
Q_A0 Q_B0 Q_H0 e The level of Q_A Q_B or Q_H respectively before the indicated steady-state input conditions were established
u QAn QGn e The level of QA or QG respectively before the most recent transition of the clock
Output
Q_H
h
Q_H0
Q_Gn
Q_Gn
Q_H0
C1995 National Semiconductor Corporation TL F 6399
RRD-B30M105 Printed in U S A