DM54L95 Datasheet, PDF (1/4 Pages) National Semiconductor (TI) – 4-Bit Parallel Access Shift Registers

June 1989
DM54L95 4-Bit Parallel Access Shift Registers
General Description
These 4-bit registers feature parallel and serial inputs paral-
lel output mode control and two clock inputs The registers
have three modes of operation
Parallel (broadside) load
Shift right (the direction Q_A toward Q_D)
Shift left (the direction Q_D toward Q_A)
Parallel loading is accomplished by applying the four bits of
data and taking the mode control input high The data is
loaded into the associated flip-flops and appears at the out-
puts after the high-to-low transition of the clock-2 input Dur-
ing loading the entry of serial data is inhibited
Shift right is accomplished on the high-to-low transition of
clock 1 when the mode control is low shift left is accom-
plished on the high-to-low transition of clock 2 when the
Connection Diagram
Dual-In-Line Package
mode control is high by connecting the output of each flip-
flop to the parallel input of the previous flip-flop (Q_D to input
C etc ) and serial data is entered at input D The clock input
may be applied simultaneously to clock 1 and clock 2 if both
modes can be clocked from the same source
Changes at the mode control input should normally be
made while both clock inputs are low however conditions
described in the last three lines of the truth table will also
ensure that register contents are protected
Features
Y _{Typical maximum clock frequency 14 MHz}
Y _{Typical power dissipation mW}
Order Number DM54L95J
or DM54L95W
See NS Package Number
J14A or W14B
Function Table
TL F 6638 – 1
Inputs
Outputs
Mode
Clocks
Serial
Control _{2 (L) 1 (R)}
A
Parallel
Q_A Q_B Q_C Q_D
B
CD
H
H
X
X
X
X
X X Q_AO Q_BO Q_CO Q_DO
H
vX
X
a
b
cda
b
c
d
H
vX
X
Q_B Q_C Q_D d Q_Bn Q_Cn Q_Dn d
L
L
H
X
X
X
X X Q_AO Q_BO Q_CO Q_DO
L
Xv
H
X
X
X X H Q_An Q_Bn Q_Cn
L
Xv
L
X
X
X X L Q_An Q_Bn Q_Cn
u
L
L
X
X
X
X X Q_AO Q_Bn Q_CO Q_DO
v
L
L
X
X
X
X X Q_AO Q_BO Q_CO Q_DO
v
L
H
X
X
X
X X Q_AO Q_BO Q_CO Q_DO
u
H
L
X
X
X
X X Q_AO Q_BO Q_CO Q_DO
u
H
H
X
X
X
X X Q_AO Q_BO Q_CO Q_DO
Shifting left requires external connection of Q_B to A Q_C to B Q_D to C Serial data is entered at input D
H e High Level (Steady State) L e Low Level (Steady State) X e Don’t Care (Any input including transitions)
v u e Transition from high to low level e Transition from low to high level
a b c d e The level of steady state input at inputs A B C or D respectively
Q_AO Q_BO Q_CO Q_DO e The level of Q_A Q_B Q_C or Q_D respectively before the indicated steady state input conditions were established
v QAn QBn QCn QDn e The level of QA QB QC or QD respectively before the most recent transition of the clock
C1995 National Semiconductor Corporation TL F 6638
RRD-B30M105 Printed in U S A