DM54L93 Datasheet, PDF (1/4 Pages) National Semiconductor (TI) – Decade, Divide-by-12, and Binary Counters

June 1989
DM54L93
Decade Divide-by-12 and Binary Counters
General Description
Each of these monolithic counters contains four master-
slave flip-flops and additional gating to provide a divide-by-
two counter and a three-stage binary counter for which the
count cycle length is divide-by-eight
To use their maximum count length (decade divide-by-
twelve or four-bit binary) the B input is connected to the Q_A
output The input count pulses are applied to input A and the
outputs are as described in the appropriate truth table
Features
Y _{Typical power dissipation 16 mW}
Y _{Count frequency 15 MHz}
Connection Diagram
Dual-In-Line Package
Function Tables
COUNT SEQUENCE
(See Note A)
TL F 6637 – 1
Order Number DM54L93J or DM54L93W
See NS Package Number J14A or W14B
Count
Output
Q_D
Q_C
Q_B
Q_A
0
L
L
L
L
1
L
L
L
H
2
L
L
H
L
3
L
L
H
H
4
L
H
L
L
5
L
H
L
H
6
L
H
H
L
7
L
H
H
H
8
H
L
L
L
9
H
L
L
H
10
H
L
H
L
11
H
L
H
H
12
H
H
L
L
13
H
H
L
H
14
H
H
H
L
15
H
H
H
H
RESET COUNT TRUTH TABLE (Note B)
Reset Inputs
Output
R0(1)
H
L
X
R0(2) Q_D Q_C Q_B Q_A
H
L
L
L
L
X
COUNT
L
COUNT
Note A Output Q_A is connected to input B
Note B H e High Level L e Low Level X e Don’t Care
C1995 National Semiconductor Corporation TL F 6637
RRD-B30M105 Printed in U S A