DM54L74 Datasheet, PDF (1/4 Pages) National Semiconductor (TI) – Dual Positive-Edge-Triggered D Flip-Flops

June 1989
DM54L74 Dual Positive-Edge-Triggered D Flip-Flops
with Preset Clear and Complementary Outputs
General Description
This device contains two independent positive-edge-trig-
gered D flip-flops with complementary outputs The informa-
tion on the D input is accepted by the flip-flops on the posi-
tive going edge of the clock pulse The triggering occurs at a
voltage level and is not directly related to the transition time
of the rising edge of the clock The data on the D input
may be changed while the clock is low or high without af-
fecting the outputs as long as the data setup and hold times
are not violated A low logic level on the preset or clear
inputs will set or reset the outputs regardless of the logic
levels of the other inputs
Connection Diagram
Dual-In-Line Package
Function Table
Order Number DM54L74J or DM54L74W
See NS Package Number J14A or W14B
TL F 6631 – 1
Inputs
Outputs
PR
CLR
CLK
D
Q
Q
L
H
X
X
H
L
H
L
X
X
L
H
L
L
X
X
H
H
H
H
u
H
H
L
H
H
u
L
L
H
H
H
L
X
Q_O
Q_O
H e High Logic Level
X e Either Low or High Logic Level
L e Low Logic Level
u e Positive-going transition
Q_O e The output logic level of Q before the indicated input conditions were
established
e This configuration is nonstable that is it will not persist when either the
preset and or clear inputs returned to their inactive (high) level
C1995 National Semiconductor Corporation TL F 6631
RRD-B30M105 Printed in U S A