DM54L72 Datasheet, PDF (1/4 Pages) National Semiconductor (TI) – AND-Gated Master-Slave J-K Flip-Flop with Preset, Clear and Complementary Outputs

June 1989
DM54L72 AND-Gated Master-Slave J-K Flip-Flop
with Preset Clear and Complementary Outputs
General Description
This device contains a positive pulse triggered master-slave
J-K flip-flop with complementary outputs Multiple J and K
inputs are ANDed together to produce the internal J and K
function for the flip-flop The J and K data is processed by
the flip-flop after a complete clock pulse While the clock is
low the slave is isolated from the master On the positive
transition of the clock the data from the AND gates is trans-
ferred to the master While the clock is high the AND gate
inputs are disabled On the negative transition of the clock
the data from the master is transferred to the slave The
logic state of the J and K inputs must not be allowed to
change while the clock is in the high state Data is trans-
ferred to the outputs on the falling edge of the clock pulse
A low logic level on the preset or clear inputs sets or resets
the outputs regardless of the logic levels of the other inputs
Connection Diagram
Dual-In-Line Package
TL F 6629 – 1
Order Number DM54L72J or DM54L72W
See NS Package Number J14A or W14B
Function Table
Inputs
Outputs
J
K
PR CLR CLK
QQ
(Note 1) (Note 1)
L
H
X
X
H
L
X
X
L
L
X
X
H
H
L
H
H
H
H
H
L
H
H
H
X
HL
X
LH
X
HH
L
Q_o Q_o
L
HL
H
LH
H
Toggle
Note 1 J e (J1)(J2)(J3) K e (K1)(K2)(K3)
H e High Logic Level
X e Either Low or High Logic Level
L e Low Logic Level
e Positive pulse The J and K inputs must be held constant while the
clock is high Data is transferred to the outputs on the falling edge of the
clock pulse
Q_o e The output logic level before the indicated input conditions were es-
tablished
e This configuration is nonstable that is it will not persist when the preset
and or clear inputs return to their inactive (high) level
Toggle e Each output changes to the complement of its previous level on
each complete high level clock pulse
C1995 National Semiconductor Corporation TL F 6629
RRD-B30M105 Printed in U S A