DM54L10 Datasheet, PDF (1/4 Pages) National Semiconductor (TI) – Triple 3-Input NAND Gates

DM54L10
Triple 3-Input NAND Gates
General Description
This device contains three independent gates each of which
performs the logic NAND function
Connection Diagram
Dual-In-Line Package
June 1989
Function Table
Order Number DM54L10J or DM54L10W
See NS Package Number J14A or W14B
Y e ABC
Inputs
Output
A
B
C
Y
X
X
L
H
X
L
X
H
L
X
X
H
H
H
H
L
H e High Logic Level
L e Low Logic Level
X e Either Low or High Logic Level
TL F 6619 – 1
C1995 National Semiconductor Corporation TL F 6619
RRD-B30M105 Printed in U S A