DM5490 Datasheet, PDF (1/10 Pages) National Semiconductor (TI) – Decade and Binary Counters

July 1992
DM5490 DM7490A DM7493A
Decade and Binary Counters
General Description
Each of these monolithic counters contains four master-
slave flip-flops and additional gating to provide a divide-by-
two counter and a three-stage binary counter for which the
count cycle length is divide-by-five for the 90A and divide-
by-eight for the 93A
All of these counters have a gated zero reset and the 90A
also has gated set-to-nine inputs for use in BCD nine’s com-
plement applications
To use their maximum count length (decade or four-bit bina-
ry) the B input is connected to the Q_A output The input
count pulses are applied to input A and the outputs are as
described in the appropriate truth table A symmetrical di-
vide-by-ten count can be obtained from the 90A counters by
connecting the Q_D output to the A input and applying the
input count to the B input which gives a divide-by-ten square
wave at output Q_A
Features
Y _{Typical power dissipation}
90A 145 mW
93A 130 mW
Y _{Count frequency 42 MHz}
Connection Diagrams
Dual-In-Line Package
TL F 6533 – 1
Order Number DM5490J DM5490W or DM7490AN
See NS Package Number J14A N14A or W14B
Dual-In-Line Package
Order Number DM7493AN
See NS Package Number N14A
TL F 6533 – 2
C1995 National Semiconductor Corporation TL F 6533
RRD-B30M105 Printed in U S A