CLC730038 Datasheet, PDF (1/6 Pages) National Semiconductor (TI) – 8-Pin Dual Op Amp Eval. Boards

N
8-Pin Dual Op Amp Eval. Boards
Part Numbers CLC730038, CLC730036
September 1997
The CLC730038 and CLC730036 evaluation
boards are designed to aid in the characterization of
Comlinear’s 8-pin, dual monolithic amplifiers.
s CLC730038 - DIP packages
Uses all through-hole components
s CLC730036 - SOIC packages
Uses all surface-mount components
Both boards have identical circuit configurations and are
designed for non-inverting gains. Inverting gains
or other circuit configurations can be obtained with slight
modifications to the boards. Use the evaluation boards
as a:
s Guide for high frequency layout
s Tool to aid in device testing and characterization
Basic Operation
Figure 1 shows the non-inverting schematic for both
boards. The input signal is brought into the board
through SMA connectors to the non-inverting input
of the amplifier. The resistor R_in is used to set the
input termination resistance to the op amp. The non-
inverting gain is set by the following equation:
Non-inverting Gain: 1+ ^Rf
R_g
The value of the feedback resistor, R_f, has a strong
influence on AC performance. Refer to the product data
sheet for feedback resistor selection. The output of the
op amp travels through a series resistance, R_out, and
then leaves the board through an SMA connector. The
series resistance, R_out, matches transmission lines or
isolates the output from capacitive loads.
1. Cut the input trace as shown in Figure 2
2. Use 25Ω for R_in
3. Terminate R_g at the input trace instead of
ground (See Figure 2)
4. Add R_t for desired input impedance (input
impedance = R_g||R_t)
Cut Here
RF1
RG1
RIN1 ^25Ω
R_t
IN1
Figure 2: Modifications for Inverting Gains
(CLC730038 board shown)
Figure 3 illustrates the inverting schematic for both
boards.
+VCC
C3
+
25Ω
Rin1
3
8
+
C1
1
Channel 1
IN1
2_-
Rg1
4 R_f1
Rt1
C2
C4
-VCC
25Ω
Rin2
OUT1
Rout1
5₊
7
OUT2
Channel 2
IN2
6_-
Rout2
Rg2
Rf2
Rt2
Select Rt to yield desired
input impedance = Rg||Rt
+VCC
C3
+
IN1
Rin1
3 ₊8
C1
1
Channel 1
2_-
4 R_f1
Rg1
C2
OUT1
Rout1
IN2
Rin2
5₊
7
Channel 2
6_-
Rf2
OUT2
Rout2
Rg2
C4
-VCC
Figure 1: Non-inverting Gain Configurations
Inverting Gain Operation
The evaluation boards can be modified to provide an
inverting gain configuration. Complete these steps to
modify the board:
Figure 3: Inverting Gain Configurations
Isolation and Channel Matching Performance
For maximum isolation between channels, proper power
supply decoupling is required. Always include the
bypass capacitors C1, C2, C3, and C4. The use of good
quality capacitors also helps to achieve better isolation
performance.
The evaluation boards have also been designed to mini-
mize channel-to-channel crosstalk. The input and output
pins of the amplifier are sensitive to the coupling of par-
asitic capacitances caused by power or ground planes
and traces. To reduce the influence of these parasitics,
the ground plane has been removed around these sen-
sitive nodes. In multilayer boards, remove both the
ground and power traces and planes around the input
and output pins.
© 1997 National Semiconductor Corporation
Printed in the U.S.A.
http://www.national.com