CLC011 Datasheet, PDF (1/8 Pages) National Semiconductor (TI) – Serial Digital Video Decoder

January 1999
CLC011
Serial Digital Video Decoder
General Description
National’s Comlinear CLC011, Serial Digital Video Decoder,
decodes and descrambles SMPTE 259M standard Serial
Digital Video datastreams with serial clock into 10-bit parallel
words and a corresponding word-rate clock. SMPTE 259M
standard parallel data is encoded and scrambled using a
9-bit shift register and is also converted from NRZ to NRZI.
The CLC011 restores the original parallel data by reversing
the encoding process. The CLC011 also extracts timing in-
formation embedded in the SDV data. These reserved code
words, known as Timing Reference Signals (TRS), indicate
the start and end of each active video line. By decoding the
TRS, the CLC011 correctly identifies the word boundaries of
the encoded input data. Detection of the TRS reserved
codes is indicated by low-true signals at the TRS and End of
Active Video (EAV) outputs.
The CLC011’s design using current-mode logic (CML) re-
duces noise injection into the power supply thereby easing
board layout and interfacing. The CMOS compatible outputs,
which feature controlled rise and fall times, may be set for ei-
ther 3.3V or 5V swings with the VDP and VCP inputs.
The CLC011 Serial Digital Video Decoder, CLC014 Adaptive
Cable Equalizer and the CLC016 Data Retiming PLL com-
bine to provide a complete Serial Digital Video receiver sys-
tem.
The CLC011 is packaged in a 28-pin PLCC.
Features
n Data decoding and deserializing
n CLC011B operates to 360Mbps
n CLC011A operates to 300Mbps
n Low noise injection to power supplies
n Single +5V or −5.2V supply operation
n Output levels programmable for interface to 5V or 3.3V
logic
n Low power
n Low cost
Block Diagram
© 1999 National Semiconductor Corporation DS100086
DS100086-1
www.national.com