CGS74LCT2524 Datasheet, PDF (1/5 Pages) National Semiconductor (TI) – 1 to 4 Minimum Skew (300 ps) 3V Clock Driver

November 2003
CGS74LCT2524
1 to 4 Minimum Skew (300 ps) 3V Clock Driver
General Description
This minimum skew clock driver is a 3V option of the current
CGS74CT2524 Minimum Skew Clock Driver and is designed
for Clock Generation and Support (CGS) applications oper-
ating at low voltage, high frequencies. This device guaran-
tees minimum output skew across the outputs of a given
device.
Skew parameters are also provided as a means to measure
duty cycle requirements as those found in high speed clock-
ing systems. This minimum skew clock driver with one input
driving four outputs, is specifically designed for signal gen-
eration and clock distribution applications.
Features
n Ideal for low power/low noise high speed applications
n Guaranteed:
— 300 ps pin-to-pin skew (t_OSHL and t_OSLH)
n Implemented on National’s FACT™ family process
n 1 input to 4 outputs low skew clock distribution
n Symmetric output current drive: 12 mA I_OH/I_OL
n Industrial temperature of −40˚C to +85˚C
n 8-pin SOIC package
n Low dynamic power consumption above 20 MHz
n Guaranteed 2 kV ESD protection
Logic Symbol
Connection Diagrams
Pin Assignment
SOIC (MO)
01195601
The output pins act as a single entity and will follow the state of the CLK
when the clock distribution chip is selected.
Pin Description
Pin Names
CLK
O₀–O₃
Description
Clock Input
Outputs
Truth Table
Inputs
CLK
L
H
L = Low Logic Level
H = High Logic Level
Outputs
O₀–O₃
L
H
01195602
01195603
See NS Package Number M08A
FACT™ is a trademark of National Semiconductor Corporation.
© 2003 National Semiconductor Corporation DS011956
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