CGS74CT2524 Datasheet, PDF (1/6 Pages) National Semiconductor (TI) – 1 to 4 Minimum Skew (300 ps) Clock Driver

September 1995
CGS74CT2524
1 to 4 Minimum Skew (300 ps) Clock Driver
General Description
These minimum skew clock drivers are designed for Clock
Generation and Support (CGS) applications operating at
high frequencies This device guarantees minimum output
skew across the outputs of a given device
Skew parameters are also provided as a means to measure
duty cycle requirements as those found in high speed clock-
ing systems The CGS74CT2524 is a minimum skew clock
driver with one input driving four outputs specifically de-
signed for signal generation and clock distribution applica-
tions
Features
Y _{Guaranteed 300 ps pin-to-pin skew (tOSHL and tOSLH)}
Y _{Implemented on National’s FACT}TM _{family process}
Y _{1 input to 4 outputs low skew clock distribution}
Y _{Symmetric output current drive 24 mA IOH IOL}
Y _{Industrial temperature of} b_{40 C to} a_{85 C}
Y _{8-pin SOIC package}
Y _{Low dynamic power consumption above 20 MHz}
Y _{Guaranteed 2 kV ESD protection}
Logic Symbol
Connection Diagrams
Pin Assignment
SOIC (M)
TL F 11752– 1
The output pins act as a single entity and will follow the state of the CLK
when the clock distribution chip is selected
Pin Description
Pin Names
CLK
O₀ – O₃
Descripton
Clock Input
Outputs
Truth Table
Inputs
CLK
L
H
L e Low Logic Level
H e High Logic Level
Outputs
O₀ – O₃
L
H
TL F 11752 – 2
TL F 11752 – 3
FACTTM is a trademark of National Semiconductor Corporation
C1995 National Semiconductor Corporation TL F 11752
RRD-B30M115 Printed in U S A