CGS74B303 Datasheet, PDF (1/6 Pages) National Semiconductor (TI) – Octal Divide-by-2 Skew Clock Driver

July 1996
CGS74B303 Octal Divide-by-2 Skew Clock Driver
General Description
These minimum skew clock drivers are designed for high
frequency Clock Generation and Support (CGS) applica-
tions These devices are ideal for duty cycle recovery appli-
cations with internal frequency divide-by-2 circuitry The de-
vices guarantee minimum skew across the outputs of a giv-
en device Skew parameters are also provided as a means
to measure duty cycle requirements as those found in high
speed clocking systems
Functional Description
The CGS74B303 contains eight flip-flops designed to have
low skew between outputs The eight outputs (six in-phase
with CLK and two out-of-phase) toggle on successive CLK
pulses PRE and CLR inputs are provided to set Q and Q
outputs high or low independent of CLK pin
Features
Y _{Clock Generation and Support (CGS) Devices ideal for}
high frequency signal generation or clock distribution
applications
Y _{Fabricated on National’s Advanced Bipolar FAST}TM _LSl
process
Y _{1 ns pin-to-pin output skew}
Y _{Specification for transition skew to meet duty cycle}
requirements
Y _{Current sourcing 24 mA and current sinking of 48 mA}
Y _{Low dynamic power consumption above 20 MHz}
Y _{Guaranteed 4 kV ESD protection}
Logic Diagram
Connection Diagram
Pin Assignment
SOlC (M)
Pin Description
Pin Names
CLK
Q₀ – Q₇
PRE
CLR
TL F 10966 – 1
TL F 10966 – 3
Description
Clock Input
Outputs
Preset
Clear
Truth Table
Inputs
Outputs
CLR
L
H
L
H
H
PRE
H
L
L
H
H
CLK
X
X
X
u
L
Q₀ – Q₅
L
H
L
Q
Q
Q₆ – Q₇
H
L
L
Q
Q
This state will not persist when CLR PRE returns to high
TRI-STATE is a registered trademark of National Semiconductor Corporation
FASTTM is a trademark of National Semiconductor Corporation
C1996 National Semiconductor Corporation TL F 10966
RRD-B30M86 Printed in U S A
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