CD4019BM Datasheet, PDF (1/4 Pages) National Semiconductor (TI) – Quad AND-OR Select Gate

February 1988
CD4019BM CD4019BC Quad AND-OR Select Gate
General Description
The CD4019BM CD4019BC is a complementary MOS quad
AND-OR select gate Low power and high noise margin
over a wide voltage range is possible through implementa-
tion of N- and P-channel enhancement mode transistors
These complementary MOS (CMOS) transistors provide the
building blocks for the 4 ‘‘AND-OR select’’ gate configura-
tions each consisting of two 2-input AND gates driving a
single 2-input OR gate Selection is accomplished by control
bits K_A and K_B All inputs are protected against static dis-
charge damage
Features
Y _{Wide supply voltage range}
Y _{High noise immunity}
Y _{Low power TTL}
compatibility
3 0V to 15V
0 45 V_DD (typ )
Fan out of 2 driving 74L
or 1 driving 74LS
Applications
Y _{AND-OR select gating}
Y _{Shift-right shift-left registers}
Y _{True complement selection}
Y _{AND OR EXCLUSIVE-OR selection}
Connection and Schematic Diagrams
Dual-In-Line Package
Order Number CD4019B
Top View
TL F 5952 – 1
Schematic diagram for 1 of 4 identical stages
C1995 National Semiconductor Corporation TL F 5952
TL F 5952 – 2
RRD-B30M105 Printed in U S A