CD40174BM Datasheet, PDF (1/6 Pages) National Semiconductor (TI) – Hex,Quad D Flip-Flop

February 1988
CD40174BM CD40174BC Hex D Flip-Flop
CD40175BM CD40175BC Quad D Flip-Flop
General Description
The CD40174B consists of six positive-edge triggered
D-type flip-flops the true outputs from each flip-flop are ex-
ternally available The CD40175B consists of four positive-
edge triggered D-type flip-flops both the true and comple-
ment outputs from each flip-flop are externally available
All flip-flops are controlled by a common clock and a com-
mon clear Information at the D inputs meeting the set-up
time requirements is transferred to the Q outputs on the
positive-going edge of the clock pulse The clearing opera-
tion enabled by a negative pulse at Clear input clears all Q
outputs to logical ‘‘0’’ and Qs (CD40175B only) to logical ‘‘1’’
All inputs are protected from static discharge by diode
clamps to V_DD and V_SS
Features
Y _{Wide supply voltage range}
3V to 15V
Y _{High noise immunity}
Y _{Low power TTL}
0 45 V_DD (typ )
fan out of 2 driving 74L
compatibility
or 1 driving 74 LS
Y _{Equivalent to MC14174B MC14175B}
Y _{Equivalent to MM74C174 MM74C175}
Connection Diagrams
CD40174B
Dual-In-Line Package
CD40175B
Dual-In-Line Package
Truth Table
Top View
TL F 5987 – 1
Order Number CD40174B or CD40175B
Top View
Inputs
Outputs
Clear
Clock
D
Q
Q
L
X
X
L
H
H
u
H
H
L
H
u
L
L
H
H
H
X
NC
NC
H
L
X
NC
NC
H e High level
L e Low level
X e Irrelevant
u e Transition from low to high level
NC e No change
e Q for CD40175B only
TL F 5987 – 2
C1995 National Semiconductor Corporation TL F 5987
RRD-B30M105 Printed in U S A