CD4015BM Datasheet, PDF (1/6 Pages) National Semiconductor (TI) – Dual 4-Bit Static Shift Register

June 1996
CD4015BM CD4015BC Dual 4-Bit Static Shift Register
General Description
The CD4015BM CD4015BC contains two identical 4-stage
serial-input parallel-output registers with independent
‘‘Data’’ ‘‘Clock ’’ and ‘‘Reset’’ inputs The logic level pres-
ent at the input of each stage is transferred to the output of
that stage at each positive-going clock transition A logic
high on the ‘‘Reset’’ input resets all four stages covered by
that input All inputs are protected from static discharge by a
series resistor and diode clamps to V_DD and V_SS
Features
Y _{Wide supply voltage range}
Y _{High noise immunity}
Y _{Low power TTL}
compatibility
Y _{Medium speed operation}
Y _{Fully static design}
3 0V to 18V
0 45 V_DD (typ )
Fan out of 2 driving 74L
or 1 driving 74LS
8 MHz (typ ) clock rate
V_DD b V_SS e 10V
Applications
Y _{Serial-input parallel-output data queueing}
Y _{Serial to parallel data conversion}
Y _{General purpose register}
Connection Diagram and Truth Table
Dual-In-Line Package
CLU D R Q₁ Q_n
L 0 0 0 Q_nb₁
L 1 0 1 Q_nb₁
K X 0 Q₁ Q_n (No change)
X X1 0 0
U Level change
X e Don’t care case
Order Number CD4015B
TL F 5948 – 1
C1996 National Semiconductor Corporation TL F 5948
RRD-B30M76 Printed in U S A
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