CD4006BC Datasheet, PDF (1/6 Pages) National Semiconductor (TI) – 18-Stage Static Shift Register

February 1988
CD4006BM CD4006BC 18-Stage Static Shift Register
General Description
The CD4006BM CD4006BC 18-stage static shift register is
comprised of four separate shift register sections two sec-
tions of four stages and two sections of five stages Each
section has an independent data input Outputs are avail-
able at the fourth stage and the fifth stage of each section
A common clock signal is used for all stages Data is shifted
to the next stage on the negative-going transition of the
clock Through appropriate connections of inputs and out-
puts multiple register sections of 4 5 8 and 9 stages or
single register sections of 10 12 13 14 16 17 and 18
stages can be implemented using one package
Features
Y _{Wide supply voltage range}
3 0V to 15V
Y _{High noise immunity}
Y _{Low power TTL}
0 45 V_DD (typ )
fan out of 2 driving 74L
compatibility
or 1 driving 74LS
Y _{Low clock input capacitance}
6 pF (typ )
Y _{Medium speed}
Y _{Low power}
10 MHz (typ ) (with V_DD e 10V)
Y _{Fully static operation}
Logic Diagrams
Connection Diagram
Dual-In-Line Package
Truth Table
TL F 5942 – 1
TL F 5942 – 3
Top View
Order Number CD4006B
TL F 5942 – 2
X e Don’t care
D e Level change
NC e No change
TL F 5942 – 4
C1995 National Semiconductor Corporation TL F 5942
RRD-B30M105 Printed in U S A