AN-2029 Datasheet, PDF (1/6 Pages) National Semiconductor (TI) – Handling & Process Recommendations

Handling & Process
Recommendations
National Semiconductor
Application Note 2029
Martin Schnepf
June 18, 2010
Introduction
This Application Note provides recommendations for han-
dling, storing and mounting of National Semiconductor’s sur-
face mount IC packages.
The final manufacturing yield and board level reliability are
influenced by various factors and processes outside the con-
trol of the IC manufacturer. This Application Note can there-
fore only be used as a guideline and reference to support our
customers. Due to the variety of possible board assembly
materials and equipments, National Semiconductor Corpora-
tion (NSC) advises the user to consult the individual suppliers
and vendors to achieve the optimum board assembly yield.
Moisture Sensitivity Level
Due to the hygroscopic nature of the plastic encapsulants, the
plastic ICs absorb a certain amount of moisture. When sub-
jecting a SMT device to reflow soldering process (e.g. in-
frared, convection, vapor phase), the entrapped moisture
inside the package can create excessive internal pressure
resulting in delamination or even cracked package (popcorn
effect).
NSC’s components that are considered moisture sensitive
are sealed in moisture barrier bags (MBB) together with a
desiccant and a Humidity Indicator Card (HIC). National
Semiconductor generally follows Industry Standards IPC/
JEDEC J-STD-020 and J-STD-033 to determine the moisture
sensitivity level and corresponding floor life time for NSC’s
plastic package types, for details on absolute maximum rat-
ings for soldering see www.national.com/ms/MS/MS-
SOLDERING.pdf.
The floor life time is the maximum time period from the open-
ing of the MBB to the final reflow soldering process. The MSL
Level and floor life time as per Table 1 is provided on NSC’s
immediate and/or intermediate packing container label. Ad-
ditionally, the MSL level and the maximum peak package
temperature for National’s devices can be found within the
Product Folder of National’s website.
TABLE 1. Moisture Sensitivity Levels (According to IPC-JEDEC J-STD-033B.1 (Note 1)
MSL Level
Time
Floor Life (out of MBB)
Conditions
1
Unlimited (no moisture barrier bag)
≤ 30ºC / 85% RH
2
1 year
≤ 30ºC / 60% RH
2A
4 weeks
≤ 30ºC / 60% RH
3
168 hours
≤ 30ºC / 60% RH
4
72 hours
≤ 30ºC / 60% RH
5
48 hours
≤ 30ºC / 60% RH
5a
24 hours
≤ 30ºC / 60% RH
6
Mandatory bake before use. After bake, must be reflowed _{≤ 30ºC / 60% RH}
within the time limit specified on the label
Storage and Shelf Life
Solderability tests were conducted on components after long
term storage in warehouse conditions and after exposure to
accelerated aging environment. Based upon the results,
NSC’s shelf life of dry-packaged moisture sensitive devices
inside the unopened moisture barrier bag is 3 years after
original seal date when stored in an environment not exceed-
ing 40ºC / 90% RH. Component storage outside the MBB
should be done in a dry storage cabinet at < 25°C and < 10%
R.H. to prevent any moisture absorption.
The shelf life with regard to soldering of non dry-packed de-
vices, i.e. MSL1, is 3 years provided the storage environment
is controlled at ≤ 30ºC / 85% RH.
Please be aware that e.g. bare die & wafer products have
different storage conditions and limitations.
Reflow Soldering
The most popular soldering method for surface mount de-
vices is forced convection reflow and therefore the topic of
this chapter. Other possible solder processes for surface
mount devices are, with restrictions, infrared reflow (IR), va-
por phase and wave soldering.
It is not possible for an IC manufacturer to provide a general
reflow profile recommendation for the end customer in charge
of the board assembly. Reflow furnace settings depend for
example on the number of heating/cooling zones, type of sol-
der paste/flux used, board and component size as well as
component density.
The actual temperature setting needs to be above the liquidus
temperature (solder melting point) of the solder paste in order
to form a reliable solder joint, while the upper limit is clearly
defined by the maximum peak package body temperature
depending on package thickness and volume as provided by
IPC /JEDEC J-STD-020, see Table 2 and Table 3
Note 1: Copyright IPC/JEDEC. Reproduced with permission.
© 2010 National Semiconductor Corporation 301141
www.national.com