AN-2001 Datasheet, PDF (1/6 Pages) National Semiconductor (TI) – The following sections will demonstrate how to achieve

Daisy Chaining Precision
DACs
National Semiconductor
Application Note 2001
Tom Domanski
September 25, 2009
1.0 Introduction
It is not uncommon for the system designer to face a quagmire
of reconciling the system complexity with the desire to keep
the system footprint small. One specific example that often
arises in the context of small system footprint is the need for
single master controller to communicate with a number of
slave devices. This is not much of a problem if the master
controller has multiple I/O resources available, and the rout-
ing of individual busses to the slave devices can be accom-
modated by ample board space. Challenge arises when the
master controller has only one I/O port available, and the sig-
nal routing space is scarce. In these cases Daisy Chaining of
slave devices may be the solution to consider.
This application note concerns exclusively the family of Pre-
cision DAC devices offered by National Semiconductor Corp.
All of the devices mentioned in this note have a unidirectional
SPI interface through which they receive data and configura-
tion commands from the master controller. However, since
the protocol details of each SPI interface differ slightly, due
care must be taken when architecting systems comprising
multiple Precision DACs.
The following sections will demonstrate how to achieve an
arbitrary number of analog output channels that are controlled
by a single 3-wire SPI interface. These expansion schemes
will exploit the Daisy Chaining capability of the 8-channel
DACs (DACxx8S085), and unique properties of the SPI in-
terface of the Micro Power family of devices (DACxx4S085,
DACxx2S085 and DACxx1S101).
2.0 Revisiting Micro Power DACs'
Digital Interface: 1, 2 and 4 Channel
Devices
The series of Micro Power DACs comprises the following
families of devices: DACxx4S085 (4 channel), DACxx2S085
(2 channel), DACxx1S101 (single channel). A typical digital
interface connectivity is shown in Figure 1. Here, a controller
transfers data into a single DAC via the unidirectional SPI bus.
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FIGURE 1. Typical Digital Interface Connectivity
A typical bus cycle is shown in Figure 2. A bus cycle is initiated
with the falling edge of SS. The DAC shifts bits presented by
MOSI into its internal shift register on each falling edge of the
SCLK, for 16 clock cycles. After the 16th falling edge the DA-
TA contained in the shift register is interpreted by the DAC’s
internal controller resulting in output level and/or mode of op-
eration update. Also, on that 16th falling edge of the CLOCK
the internal SCLK and D_IN busses of the DAC are gated off
and therefore any further DATA present at D_IN pin, or SCLK
pulse, is ignored.
The SS signal can be raised again any time after 16th falling
edge. Subsequent DATA transfers will commence with the
falling edge of the SS.
FIGURE 2. Typical Bus Cycle
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