ADC16DV160 Datasheet, PDF (1/26 Pages) National Semiconductor (TI) – Dual Channel, 16-Bit, 160 MSPS Analog-to-Digital Converter with DDR LVDS Outputs

ADC16DV160
PRELIMINARY
August 17, 2009
Dual Channel, 16-Bit, 160 MSPS Analog-to-Digital
Converter with DDR LVDS Outputs
General Description
The ADC16DV160 is a monolithic dual channel high perfor-
mance CMOS analog-to-digital converter capable of convert-
ing analog input signals into 16-bit digital words at rates up to
160 Mega Samples Per Second (MSPS). This converter uses
a differential, pipelined architecture with digital error correc-
tion and an on-chip sample-and-hold circuit to minimize pow-
er consumption and external component count while provid-
ing excellent dynamic performance. Automatic power-up
calibration enables excellent dynamic performance and re-
duces part-to-part variation, and the ADC16DV160 can be re-
calibrated at any time through the 3-wire Serial Peripheral
Interface (SPI). An integrated low noise and stable voltage
reference and differential reference buffer amplifier eases
board level design. The on-chip duty cycle stabilizer with low
additive jitter allows a wide range of input clock duty cycles
without compromising dynamic performance. A unique sam-
ple-and-hold stage yields a full-power bandwidth of 1.4 GHz.
The interface between the ADC16DV160 and a receiver block
can be easily verified and optimized via fixed pattern gener-
ation and output clock position features. The digital data is
provided via dual data rate LVDS outputs – making possible
the 68-pin, 10 mm x 10 mm LLP package. The ADC16DV160
operates on dual power supplies of +1.8V and +3.0V with a
power-down feature to reduce power consumption to very low
levels while allowing fast recovery to full operation.
■ ^{On-chip low jitter duty-cycle stabilizer}
■ ^{Power-down and sleep modes}
■ ^{Output fixed pattern generation}
■ ^{Output clock position adjustment}
■ ^{3-wire SPI}
■ ^{Offset binary or 2's complement data format}
■ ^{68-pin LLP package (10x10x0.8, 0.5mm pin-pitch)}
Key Specifications
■ ^Resolution
■ ^{Conversion Rate}
■ ^SNR
(@F_IN = 30 MHz)
(@F_IN = 197 MHz)
■ ^SFDR
(@F_IN = 30 MHz)
(@F_IN = 197 MHz)
■ ^{Full Power Bandwidth}
■ ^{Power Consumption}
-Core per channel
-LVDS Driver
-Total
■ ^{Operating Temperature Range}
16 Bits
160 MSPS
  
78.5 dBFS (typ)
76.3 dBFS (typ)
  
95 dBFS (typ)
91.2 dBFS (typ)
1.4 GHz (typ)
  
591 mW (typ)
118 mW (typ)
1.3W (typ)
-40°C ~ 85°C
Features
■ ^{Low power consumption}
■ ^{On-chip precision reference and sample-and-hold circuit}
■ ^{On-chip automatic calibration during power-up}
■ ^{Dual data rate LVDS output port}
■ ^{Dual Supplies: 1.8V and 3.0V operation}
■ ^{Selectable input range: 2.4, 2.0, 1.5 and 1.0V}_PP
■ ^{Sampling edge flipping with clock divider by 2 option}
■ ^{Integer clock divider by 1 or 2}
Applications
■ ^{Multi-carrier, Multi-standard Base Station Receivers}
-MC-GSM/EDGE, CDMA2000, UMTS, LTE and WiMAX
■ ^{High IF Sampling Receivers}
■ ^{Diversity Channel Receivers}
■ ^{Test and Measurement Equipment}
■ ^{Communications Instrumentation}
■ ^{Portable Instrumentation}
© 2009 National Semiconductor Corporation 301014
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