ADC14V155_08 Datasheet, PDF (1/22 Pages) National Semiconductor (TI) – 14-Bit, 155 MSPS, 1.1 GHz Bandwidth A/D Converter with LVDS Outputs

May 23, 2008
ADC14V155
14-Bit, 155 MSPS, 1.1 GHz Bandwidth A/D Converter with
LVDS Outputs
General Description
The ADC14V155 is a high-performance CMOS analog-to-
digital converter with LVDS outputs. It is capable of converting
analog input signals into 14-Bit digital words at rates up to 155
Mega Samples Per Second (MSPS). Data leaves the chip in
a DDR (Dual Data rate) format; this allows both edges of the
output clock to be utilized while achieving a smaller package
size. This converter uses a differential, pipelined architecture
with digital error correction and an on-chip sample-and-hold
circuit to minimize power consumption and the external com-
ponent count, while providing excellent dynamic perfor-
mance. A unique sample-and-hold stage yields a full-power
bandwidth of 1.1 GHz. The ADC14V155 operates from dual
+3.3V and +1.8V power supplies and consumes 951 mW of
power at 155 MSPS.
The separate +1.8V supply for the digital output interface al-
lows lower power operation with reduced noise. A power-
down feature reduces the power consumption to 15 mW while
still allowing fast wake-up time to full operation. In addition
there is a sleep feature which consumes 50 mW of power and
has a faster wake-up time.
The differential inputs provide a full scale differential input
swing equal to 2 times the reference voltage. A stable 1.0V
internal voltage reference is provided, or the ADC14V155 can
be operated with an external reference.
Clock mode (differential versus single-ended) and output data
format (offset binary versus 2's complement) are pin-se-
lectable. A duty cycle stabilizer maintains performance over
a wide range of input clock duty cycles.
The ADC14V155 is pin-compatible with the ADC12V170. It is
available in a 48-lead LLP package and operates over the
industrial temperature range of −40°C to +85°C.
Features
■ ^{1.1 GHz Full Power Bandwidth}
■ ^{Internal sample-and-hold circuit}
■ ^{Low power consumption}
■ ^{Internal precision 1.0V reference}
■ ^{Single-ended or Differential clock modes}
■ ^{Clock Duty Cycle Stabilizer}
■ ^{Dual +3.3V and +1.8V supply operation}
■ ^{Power-down and Sleep modes}
■ ^{Offset binary or 2's complement output data format}
■ ^{Dual Data Rate (DDR) LVDS outputs}
■ ^{Pin-compatible: ADC12V170}
■ ^{48-pin LLP package, (7x7x0.8mm, 0.5mm pin-pitch)}
Key Specifications
■ ^Resolution
■ ^{Conversion Rate}
■ ^{SNR (f}_IN ^{= 70 MHz)}
■ ^{SFDR (f}_IN ^{= 70 MHz)}
■ ^{ENOB (f}_IN ^{= 70 MHz)}
■ ^{Full Power Bandwidth}
■ ^{Power Consumption}
14 Bits
155 MSPS
71.7 dBFS (typ)
86.9 dBFS (typ)
11.5 bits (typ)
1.1 GHz (typ)
951 mW (typ)
Applications
■ ^{High IF Sampling Receivers}
■ ^{Wireless Base Station Receivers}
■ ^{Power Amplifier Linearization}
■ ^{Multi-carrier, Multi-mode Receivers}
■ ^{Test and Measurement Equipment}
■ ^{Communications Instrumentation}
■ ^{Radar Systems}
Block Diagram
© 2008 National Semiconductor Corporation 300052
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