ADC14DC080 Datasheet, PDF (1/14 Pages) National Semiconductor (TI) – Dual 14-Bit, 80/105 MSPS A/D Converter with CMOS Outputs

ADVANCE INFORMATION
September 2007
ADC14DC080/ADC14DC105
Dual 14-Bit, 80/105 MSPS A/D Converter with CMOS
Outputs
General Description
NOTE: This is Advance Information for products current-
ly in development. ALL specifications are design targets
and are subject to change.
The ADC14DC080 and ADC14DC105 are high-performance
CMOS analog-to-digital converters capable of converting two
analog input signals into 14-bit digital words at rates up to
80/105 Mega Samples Per Second (MSPS) respectively.
These converters use a differential, pipelined architecture
with digital error correction and an on-chip sample-and-hold
circuit to minimize power consumption and the external com-
ponent count, while providing excellent dynamic perfor-
mance. A unique sample-and-hold stage yields a full-power
bandwidth of 1 GHz. The ADC14DC080/105 may be operated
from a single +3.3V power supply. A power-down feature re-
duces the power consumption to very low levels while still
allowing fast wake-up time to full operation. The differential
inputs provide a 2V full scale differential input swing. A stable
1.2V internal voltage reference is provided, or the AD-
C14DC080/105 can be operated with an external 1.2V refer-
ence. Output data format (offset binary versus 2's comple-
ment) and duty cycle stabilizer are pin-selectable. The duty
cycle stabilizer maintains performance over a wide range of
clock duty cycles.
The ADC14DC080/105 is available in a 60-lead LLP package
and operates over the industrial temperature range of −40°C
to +85°C.
Features
■ ^{1 GHz Full Power Bandwidth}
■ ^{Internal sample-and-hold circuit and precision reference}
■ ^{Low power consumption}
■ ^{Clock Duty Cycle Stabilizer}
■ ^{Single +3.3V supply operation}
■ ^{Power-down mode}
■ ^{Offset binary or 2's complement output data format}
■ ^{60-pin LLP package, (9x9x0.8mm, 0.5mm pin-pitch)}
Key Specifications
■ ^{For ADC14DC105}
■ ^Resolution
■ ^{Conversion Rate}
■ ^{SNR (f}_IN ^{= 240 MHz)}
■ ^{SFDR (f}_IN ^{= 240 MHz)}
■ ^{Full Power Bandwidth}
■ ^{Power Consumption}
14 Bits
105 MSPS
72 dBFS (typ)
83 dBFS (typ)
1 GHz (typ)
800 mW (typ)
Applications
■ ^{High IF Sampling Receivers}
■ ^{Wireless Base Station Receivers}
■ ^{Test and Measurement Equipment}
■ ^{Communications Instrumentation}
■ ^{Portable Instrumentation}
Connection Diagram
© 2007 National Semiconductor Corporation 300101
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