ADC14C065 Datasheet, PDF (1/17 Pages) National Semiconductor (TI) – 14-Bit, 65/80/95/105 MSPS A/D Converter

ADVANCE INFORMATION
September 2006
ADC14C065/ADC14C080/ADC14C095/ADC14C105
14-Bit, 65/80/95/105 MSPS A/D Converter
General Description
NOTE: This is Advance Information for products cur-
rently in development. ALL specifications are design
targets and are subject to change.
The ADC14C065, ADC14C080, ADC14C095, and
ADC14105 are high-performance CMOS analog-to-digital
converters capable of converting analog input signals into
14-bit digital words at rates up to 65/80/95/105 Mega
Samples Per Second (MSPS) respectively. These convert-
ers use a differential, pipelined architecture with digital error
correction and an on-chip sample-and-hold circuit to mini-
mize power consumption and the external component count,
while providing excellent dynamic performance. A unique
sample-and-hold stage yields a full-power bandwidth of 1
GHz. The ADC14C065/080/095/105 may be operated from a
single +3.3V power supply and consumes low power.
A separate +2.5V supply may be used for the digital output
interface which allows lower power operation with reduced
noise. A power-down feature reduces the power consump-
tion to very low levels while still allowing fast wake-up time to
full operation. The differential inputs provide a 2V full scale
differential input swing. A stable 1.2V internal voltage refer-
ence is provided, or the ADC14C065/080/095/105 can be
operated with an external 1.2V reference. Output data for-
mat (offset binary versus 2’s complement) and duty cycle
stabilizer are pin-selectable. The duty cycle stabilizer main-
tains performance over a wide range of clock duty cycles.
The ADC14C065/080/095/105 is available in a 32-lead LLP
package and operates over the industrial temperature range
of −40˚C to +85˚C.
Features
n 1 GHz Full Power Bandwidth
n Internal sample-and-hold circuit
n Low power consumption
n Internal precision reference
n Data Ready output clock
n Clock Duty Cycle Stabilizer
n Single +3.3V supply operation
n Power-down mode
n Offset binary or 2’s complement output data format
n 32-pin LLP package, (5x5x0.8mm, 0.5mm pin-pitch)
Key Specifications
n For ADC14C105
n Resolution
n Conversion Rate
n SNR (f_IN = 240 MHz)
n SFDR (f_IN = 240 MHz)
n Full Power Bandwidth
n Power Consumption
14 Bits
105 MSPS
72 dBFS (typ)
83 dBFS (typ)
1 GHz (typ)
400 mW (typ)
Applications
n High IF Sampling Receivers
n Wireless Base Station Receivers
n Test and Measurement Equipment
n Communications Instrumentation
n Portable Instrumentation
Connection Diagram
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