ADC14155QML Datasheet, PDF (1/26 Pages) National Semiconductor (TI) – 14-Bit, 155 MSPS, 1.1 GHz Bandwidth A/D Converter

ADC14155QML
June 15, 2009
14-Bit, 155 MSPS, 1.1 GHz Bandwidth A/D Converter
General Description
The ADC14155 is a high-performance CMOS analog-to-dig-
ital converter capable of converting analog input signals into
14-bit digital words at rates up to 155 Mega Samples Per
Second (MSPS). This converter uses a differential, pipelined
architecture with digital error correction and an on-chip sam-
ple-and-hold circuit to minimize power consumption and the
external component count, while providing excellent dynamic
performance. A unique sample-and-hold stage yields a full-
power bandwidth of 1.1 GHz. The ADC14155 operates from
dual +3.3V and +1.8V power supplies and consumes 967 mW
of power at 155 MSPS.
The separate +1.8V supply for the digital output interface al-
lows lower power operation with reduced noise. A power-
down feature reduces the power consumption to 5 mW with
the clock input disabled, while still allowing fast wake-up time
to full operation.
The differential inputs provide a full scale differential input
swing equal to 2 times the reference voltage. A stable 1.0V
internal voltage reference is provided, or the ADC14155 can
be operated with an external reference.
The ADC14155 can be configured for either single-ended or
differential operation. Clock mode (differential versus single-
ended) and output data format (offset binary versus 2's com-
plement) are pin-selectable. A duty cycle stabilizer maintains
performance over a wide range of clock duty cycles.
The ADC14155 is available in a 48-lead thermally ehanced
mult-layer ceramic quad package and operates over the mil-
itary temperature range of -55°C to +125°C.
Features
■ ^{Total Ionizing Dose}
100 krad(Si)
■ ^{Single Event Latch-up}
120 MeV-cm²/mg
■ ^{1.1 GHz Full Power Bandwidth}
■ ^{Internal sample-and-hold circuit}
■ ^{Low power consumption}
■ ^{Internal precision 1.0V reference}
■ ^{Single-ended or Differential clock modes}
■ ^{Data Ready output clock}
■ ^{Clock Duty Cycle Stabilizer}
■ ^{Dual +3.3V and +1.8V supply operation (+/- 10%)}
■ ^{Power-down mode}
■ ^{Offset binary or 2's complement output data format}
■ ^{48-pin Cer Quad package, (11.5mm x 11.5mm, 0.635mm}
pin-pitch)
Key Specifications
■ ^Resolution
■ ^{Conversion Rate}
■ ^{SNR (f}_IN ^{= 70 MHz)}
■ ^{SFDR (f}_IN ^{= 70 MHz)}
■ ^{ENOB (f}_IN ^{= 70 MHz)}
■ ^{Full Power Bandwidth}
■ ^{Power Consumption}
14 Bits
155 MSPS
70.1 dBFS (typ)
82.3 dBFS (typ)
11.3 bits (typ)
1.1 GHz (typ)
967 mW (typ)
Applications
■ ^{High IF Sampling Receivers}
■ ^{Power Amplifier Linearization}
■ ^{Multi-carrier, Multi-mode Receivers}
■ ^{Test and Measurement Equipment}
■ ^{Communications Instrumentation}
■ ^{Radar Systems}
Ordering Information
NS Part Number
ADC14155W-MLS
ADC14155WRQV
(Note 15)
SMD Part Number
TBD
NS Package Number
EL48A
EL48A
Package Description
48L Cer Quad
48L Cer Quad
© 2009 National Semiconductor Corporation 202107
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