ADC12QS065 Datasheet, PDF (1/18 Pages) National Semiconductor (TI) – Quad 12-Bit 65 MSPS A/D Converter with LVDS Serialized Outputs

PRELIMINARY
November 2005
ADC12QS065
Quad 12-Bit 65 MSPS A/D Converter with LVDS
Serialized Outputs
General Description
This is Preliminary Information for a product currently in
development. ALL specifications are design targets and
are subject to change.
The ADC12QS065 is a low power, high performance CMOS
4-channel analog-to-digital converter with LVDS serialized
outputs. The ADC12QS065 digitizes signals to 12 bits reso-
lution at sampling rates up to 65 MSPS while consuming a
typical 200 mW/ADC from a single 3.0V supply. Sampled
data is transformed into high speed serial LVDS output data
streams. Clock and frame LVDS pairs aid in data capture.
The ADC12QS065’s six differential pairs transmit data over
backplanes or cable and also make PCB design easier. In
addition, the reduced cable, PCB trace count, and connector
size tremendously reduce cost.
No missing codes performance is guaranteed over the full
operating temperature range. The pipeline ADC architecture
achieves >11 Effective Bits over the entire Nyquist band at
65 MSPS.
The ADC12QS065 output pins can be put into a high imped-
ance state. The serializer PLL can lock to frequencies be-
tween 20 MHz and 65 MHz.
When not converting, power consumption can be reduced by
pulling the PD (Power Down) pin high, placing the converter
into a low power state where it typically consumes less than
3 mW total, and from which recovery is less than 5 ms. The
ADC12QS065’s speed, resolution and single supply opera-
tion makes it well suited for a variety of applications in
ultrasound, imaging, video and communications. Operating
over the industrial (-40˚C to +85˚C) temperature range, the
ADC12QS065 is available in a 64 pin TQFP package.
Features
n Single +3.0V supply operation
n Internal sample-and-hold
n Internal reference
n Low power consumption
n Power down mode
n Clock and Data Frame Timing
n 780 Mbps serial LVDS data rate (at 65 MHz clock)
n LVDS serial output rated for 100 Ohm load
Key Specifications
n Resolution
n DNL
n SNR (f_IN = 10 MHz)
n SFDR (f_IN = 10 MHz)
n ENOB (at Nyquist)
n Power Consumption
n -- Operating, 65 MSPS, per ADC
n -- Power Down Mode
12 Bits
±0.3 LSB (typ)
68.5 dB (typ)
85 dB (typ)
11 Bits (typ)
200 mW (typ)
< 3 mW (typ)
Applications
n Ultrasound
n Medical Imaging
n Communications
n Portable Instrumentation
n Digital Video
Connection Diagram
© 2005 National Semiconductor Corporation DS201068
20106801
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