ADC12DL080 Datasheet, PDF(1/24 Page) National Semiconductor (TI) – Dual 12-Bit, 80 MSPS, A/D Converter for IF Sampling

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ADC12DL080 Datasheet, PDF (1/24 Pages) National Semiconductor (TI) – Dual 12-Bit, 80 MSPS, A/D Converter for IF Sampling

February 2006

ADC12DL080

Dual 12-Bit, 80 MSPS, A/D Converter for IF Sampling

General Description

The ADC12DL080 is a dual, low power monolithic CMOS

analog-to-digital converter capable of converting analog in-

put signals into 12-bit digital words at 80 Megasamples per

second (MSPS). This converter uses a differential, pipeline

architecture with digital error correction and an on-chip

sample-and-hold circuit to minimize power consumption

while providing excellent dynamic performance and a 600

MHz Full Power Bandwidth. Operating on a single +3.3V

power supply, the ADC12DL080 achieves 11.0 effective bits

at Nyquist and consumes just 447mW at 80 MSPS. The

Power Down feature reduces power consumption to 50 mW.

The differential inputs provide a full scale differential input

swing equal to 2 times VREF with the possibility of a single-

ended input. Full use of the differential input is recom-

mended for optimum performance. Duty cycle stabilization

and output data format are selectable. The output data can

be set for offset binary or twoâs complement.

To ease interfacing to lower voltage systems, the digital

output driver power pins of the ADC12DL080 can be con-

nected to a separate supply voltage in the range of 2.4V to

the analog supply voltage. This device is available in the

64-lead TQFP package and will operate over the industrial

temperature range of â40ËC to +85ËC. An evaluation board is

available to ease the evaluation process.

Features

n Single +3.3V supply operation

n Internal sample-and-hold

n Internal or External reference

n Outputs 2.4V to 3.6V compatible

n Power down mode

n Duty Cycle Stabilizer

n Pin compatible with ADC12DL040, ADC12DL065,

ADC12DL066

Key Specifications

n Resolution

n Max Conversion Rate

n DNL

n SNR (fIN=40MHz)

n SNR (fIN=200MHz)

n SFDR (fIN=40MHz)

n SFDR (fIN=200MHz)

n Power Consumption

â Operating

â Power Down Mode

12 Bits

80 MSPS

Â±0.4 LSB (typ)

69 dB (typ)

67 dB (typ)

82 dB (typ)

81 dB (typ)

447 mW (typ)

50 mW (typ)

Applications

n Instrumentation

n Communications Receivers

n Sonar/Radar

n xDSL, Cable Modems

Connection Diagram

TRI-STATEÂ® is a registered trademark of National Semiconductor Corporation.

20169401

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