ADC12D1XXX Datasheet, PDF (1/10 Pages) National Semiconductor (TI) – Synchronizing Multiple GSPS ADCs in a System: The AutoSync Feature

Synchronizing Multiple
GSPS ADCs in a System:
The AutoSync Feature
National Semiconductor
Application Note 2132
Marjorie Plisch
May 10, 2011
The AutoSync feature, new on National’s
10- and 12-bit GSPS ADC family, is capable of synchronizing
the data at the output of multiple ADCs in a system. The novel
architecture of this feature departs significantly from previous
DCLK reset style solutions and has considerable advantages.
This Applications Note covers an overview of synchroniza-
tion, implementation of the feature, and FAQs. See Figure 1
for an example. For this Apps Note, "ADC" refers to the AD-
C12D1800/1600/1000 and the ADC10D1500/1000.
FIGURE 1. Synchronizing Multiple ADCs using AutoSync
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Overview of Synchronization
THE GOAL: SYNCHRONIZING MULTIPLE ADCS
The purpose of the AutoSync feature is to facilitate aligning
the Data and DCLKs of multiple ADCs in a system, as illus-
trated in Figure 2.
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FIGURE 2. Multiple ADCs in a System
In general, this feature is useful in systems where the rela-
tionships of the analog inputs to each ADC, with respect to
one another, must be known. The two most general cases are
(1) when all ADCs in the system must sample multiple inputs
at the same time and (2) when the ADCs in the system must
sample the input with a known phase relationship with respect
to one another. An example of the first case is a 4-channel
oscilloscope which must simultaneously sample and display
each analog input. For the second case, any system in which
the ADCs are interleaved requires that their data output are
aligned with a known phase relationship in order to correctly
interleave the data in digital post-processing. In both cases,
the inputs may be designed to arrive at each ADC with the
desired relationship with respect to one another and the Sam-
pling Clock may arrive at each ADC at the same time, but if
the converted data at each ADC output has an unknown re-
lationship with respect to the other ADC outputs, then the
critical information which was carefully set up at analog inputs
and Sampling Clocks, would be lost.
THE PROBLEM: UNSYNCHRONIZED DCLKS
It is not guaranteed by design whether the rising Sampling
Clock edge which samples the data will generate a rising or
falling DCLK transition when data appears at the output. For
the Demux Mode, it is also not certain which one of two Sam-
pling Clock edges will generate the DCLK (and Data). In order
to completely synchronize the DCLKs, three requirements
must be met: (1) the Sampling Clock must arrive to each ADC
at the same instant; (2) each DCLK must be generated from
the same edge of the Sampling Clock; (3) the phase of each
DCLK must be the same. DCLK is generated from the Sam-
pling Clock, which is why the Sampling Clock must arrive to
each ADC at the same time. Any delta in the arrival of the
Sampling Clocks translates to the same delta between
DCLKs. For 1:2 Demux Mode, in which the output Data is
produced on two 12-bit busses at half the non-demultiplexed
rate, the DCLK runs at ¼ the rate of the Sampling Clock, a.k.a.
© 2011 National Semiconductor Corporation 301545
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