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ADC11DV200 Datasheet, PDF (1/24 Pages) National Semiconductor (TI) – Dual 11-bit, 200 MSPS Low-Power A/D Converter with Parallel LVDS/CMOS Outputs
ADC11DV200
April 23, 2009
Dual 11-bit, 200 MSPS Low-Power A/D Converter with
Parallel LVDS/CMOS Outputs
General Description
The ADC11DV200 is a monolithic analog-to-digital converter
capable of converting two analog input signals into 11-bit dig-
ital words at rates up to 200 Mega Samples Per Second
(MSPS). The digital output mode is selectable and can be ei-
ther differential LVDS or CMOS signals. This converter uses
a differential, pipelined architecture with digital error correc-
tion and an on-chip sample-and-hold circuit to minimize die
size and power consumption while providing excellent dy-
namic performance. A unique sample-and-hold stage yields
a full-power bandwidth of 900MHz. Fabricated in core CMOS
process, the ADC11DV200 may be operated from a single
1.8V power supply. The ADC11DV200 achieves approxi-
mately 10.06 effective bits at Nyquist and consumes just
280mW at 170MSPS in CMOS mode 450mW at 200MSPS in
LVDS mode. The power consumption can be scaled down
further by reducing sampling rates.
Applications
■ Digital Predistortion (DPD)
■ Wireless Communications Infrastructure
■ Medical Imaging
■ Portable Instrumentation
■ Digital Video
Features
■ Single 1.8V power supply operation.
■ Power scaling with clock frequency.
■ Internal sample-and-hold.
■ Internal or external reference.
■ Power down mode.
■ Offset binary or 2's complement output data format.
■ LVDS or CMOS output signals.
■ 60-pin LLP package, (9x9x0.8mm, 0.5mm pin-pitch)
■ Clock Duty Cycle Stabilizer.
■ IF Sampling Bandwidth > 900MHz.
Key Specifications
■ Resolution
11 Bits
■ Conversion Rate
200 MSPS
■ ENOB
10.06 bits (typ) @Fin=70MHz
■ SNR
62.5 dBFS (typ) @Fin=70MHz
■ SINAD
62.3 dBFS (typ) @Fin=70MHz
■ SFDR
82 dBFS (typ) @Fin=70MHz
■ LVDS Power
450 mW (typ) @Fs=200 MSPS
■ CMOS Power
280 mW (typ) @Fs=170 MSPS
■ Operating Temp. Range
−40°C to +85°C.
Block Diagram
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