ADC11DL066 Datasheet, PDF(1/23 Page) National Semiconductor (TI) – Dual 11-Bit, 66 MSPS, 450 MHz Input Bandwidth A/D Converter w/Internal Reference

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ADC11DL066 Datasheet, PDF (1/23 Pages) National Semiconductor (TI) – Dual 11-Bit, 66 MSPS, 450 MHz Input Bandwidth A/D Converter w/Internal Reference

March 2004

ADC11DL066

Dual 11-Bit, 66 MSPS, 450 MHz Input Bandwidth A/D

Converter w/Internal Reference

General Description

The ADC11DL066 is a dual, low power monolithic CMOS

analog-to-digital converter capable of converting analog in-

put signals into 11-bit digital words at 66 Megasamples per

second (MSPS), minimum. This converter uses a differential,

pipeline architecture with digital error correction and an on-

chip sample-and-hold circuit to minimize die size and power

consumption while providing excellent dynamic performance

and a 450 MHz Full Power Bandwidth. Operating on a single

3.3V power supply, the ADC11DL066 achieves 10.3 effective

bits and consumes just 686 mW at 66 MSPS, including the

reference current. The Power Down feature reduces power

consumption to 75 mW.

The differential inputs provide a full scale differential input

swing equal to 2 times VREF with the possibility of a single-

ended input. Full use of the differential input is recom-

mended for optimum performance. The digital outputs from

the two ADCs are available on separate 11-bit buses with an

output data format choice of offset binary or twoâs comple-

ment.

To ease interfacing to lower voltage systems, the digital

output driver power pins of the ADC11DL066 can be con-

nected to a separate supply voltage in the range of 2.4V to

the digital supply voltage.

This device is available in the 64-lead TQFP package and

will operate over the industrial temperature range of â40ËC to

+85ËC. An evaluation board is available to ease the evalua-

tion process.

Features

n Single +3.3V supply operation

n Internal sample-and-hold

n Outputs 2.4V to 3.3V compatible

n Power down mode

n On-chip reference

Key Specifications

n Resolution

n DNL

n SNR (fIN = 10 MHz)

n SFDR (fIN = 10 MHz)

n Data Latency

n Power Consumption

â Operating

â Power Down

Applications

n Ultrasound and Imaging

n Instrumentation

n Communications Receivers

n Sonar/Radar

n xDSL

n Cable Modems

n DSP Front Ends

11 Bits

Â±0.25 LSB (typ)

64 dB (typ)

80 dB (typ)

6 Clock Cycles

686 mW (typ)

75 mW (typ)

Connection Diagram

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