ADC10D040 Datasheet, PDF (1/28 Pages) National Semiconductor (TI) – Dual 10-Bit, 40 MSPS, 267 mW A/D Converter

February 2005
ADC10D040
Dual 10-Bit, 40 MSPS, 267 mW A/D Converter
General Description
The ADC10D040 is a dual low power, high performance
CMOS analog-to-digital converter that digitizes signals to 10
bits resolution at sampling rates up to 45 MSPS while con-
suming a typical 267 mW from a single 3.3V supply. No
missing codes is guaranteed over the full operating tempera-
ture range. The unique two stage architecture achieves 9.4
Effective Bits over the entire Nyquist band at 40 MHz sample
rate. An output formatting choice of offset binary or 2’s
complement coding and a choice of two gain settings eases
the interface to many systems. Also allowing great flexibility
of use is a selectable 10-bit multiplexed or 20-bit parallel
output mode. An offset correction feature minimizes the off-
set error.
To ease interfacing to most low voltage systems, the digital
output power pins of the ADC10D040 can be tied to a
separate supply voltage of 1.5V to 3.6V, making the outputs
compatible with other low voltage systems. When not con-
verting, power consumption can be reduced by pulling the
PD (Power Down) pin high, placing the converter into a low
power state where it typically consumes less than 1 mW and
from which recovery is less than 1 ms. Bringing the STBY
(Standby) pin high places the converter into a standby mode
where power consumption is about 30 mW and from which
recovery is 800 ns.
The ADC10D040’s speed, resolution and single supply op-
eration make it well suited for a variety of applications,
including high speed portable applications.
Operating over the industrial (−40˚ ≤ T_A ≤ +85˚C) tempera-
ture range, the ADC10D040 is available in a 48-pin TQFP. An
evaluation board is available to ease the design effort.
Features
n Internal sample-and-hold
n Internal Reference Capability
n Dual gain settings
n Offset correction
n Selectable offset binary or 2’s complement output
n Multiplexed or parallel output bus
n Single +3.0V to 3.6V operation
n Power down and standby modes
n 3V TTL Logic input/output compatible
Key Specifications
n Resolution
10 Bits
n Conversion Rate
40 MSPS
n ENOB
9.4 Bits (typ)
n DNL
0.35 LSB (typ)
n Conversion Latency Parallel Outputs 2.5 Clock Cycles
— Multiplexed Outputs, I Data Bus 2.5 Clock Cycles
— Multiplexed Outputs, Q Data Bus
3 Clock Cycles
n PSRR
90 dB
n Power Consumption — Normal Operation 267 mW (typ)
— Power Down Mode
< 1 mW (typ)
— Fast Recovery Standby Mode
30 mW (typ)
Applications
n Digital Video
n CCD Imaging
n Portable Instrumentation
n Communications
n Medical Imaging
n Ultrasound
© 2005 National Semiconductor Corporation DS200297
www.national.com