ADC08D1000QML Datasheet, PDF (1/44 Pages) National Semiconductor (TI) – High Performance, Low Power, Dual 8-Bit, 1 GSPS A/D Converter

ADC08D1000QML
November 9, 2009
High Performance, Low Power, Dual 8-Bit, 1 GSPS A/D
Converter
General Description
The ADC08D1000 is a dual, low power, high performance
CMOS analog-to-digital converter that digitizes signals to 8
bits resolution at sampling rates up to 1.2 GSPS. Consuming
a typical 1.6 Watts at 1 GSPS from a single 1.9 Volt supply,
this device is guaranteed to have no missing codes over the
full operating temperature range. The unique folding and in-
terpolating architecture, the fully differential comparator de-
sign, the innovative design of the internal sample-and-hold
amplifier and the self-calibration scheme enable a very flat
response of all dynamic parameters beyond Nyquist, produc-
ing a high 7.4 Effective Number Of Bits (ENOB) with a 498
MHz input signal and a 1 GHz sample rate while providing a
10^-18 Bit Error Rate ( B.E.R.). Output formatting is offset binary
and the Low Voltage Differential Signaling (LVDS) digital out-
puts are compliant with IEEE 1596.3-1996, with the exception
of an adjustable common mode voltage between 0.8V and
1.13V.
Each converter has a 1:2 demultiplexer that feeds two LVDS
buses and reduces the output data rate on each bus to half
the sampling rate. The two converters can be interleaved and
used as a single 2 GSPS ADC.
The converter typically consumes less than 3.5 mW in the
Power Down Mode and is available in a 128-lead, thermally
enhanced multi-layer ceramic quad package and operates
over the Military (-55°C ≤ T_A ≤ +125°C) temperature range.
This part will work in a radiation environment, with ex-
cellent results, provided the guidelines in applications
section 2.1 are followed.
Features
■ ^{Total Ionizing Dose}
300 krad(Si)
■ ^{Single Event Latch-Up}
>120 MeV/mg/cm²
■ ^{Internal Sample-and-Hold}
■ ^{Single +1.9V ±0.1V Operation}
■ ^{Choice of SDR or DDR output clocking}
■ ^{Interleave Mode for 2x Sampling Rate}
■ ^{Multiple ADC Synchronization Capability}
■ ^{Guaranteed No Missing Codes}
■ ^{Serial Interface for Extended Control}
■ ^{Fine Adjustment of Input Full-Scale Range and Offset}
■ ^{Duty Cycle Corrected Sample Clock}
Key Specifications
■ ^Resolution
■ ^{Max Conversion Rate}
■ ^{Bit Error Rate}
■ ^{ENOB @ 498 MHz Input}
■ ^DNL
■ ^{Power Consumption}
— Operating
— Power Down Mode
8 Bits
1 GSPS (min)
10^-18 (typ)
7.4 Bits (typ)
±0.15 LSB (typ)
1.6 W (typ)
3.5 mW (typ)
Applications
■ ^{Communication Satellites/Systems}
■ ^{Direct RF Down Conversion}
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