74LVX373 Datasheet, PDF (1/8 Pages) Fairchild Semiconductor – Low Voltage Octal Transparent Latch with 3-STATE Outputs

January 1996
74LVX373
Low Voltage Octal Transparent Latch
with TRI-STATE Outputs
General Description
The LVX373 consists of eight latches with TRI-STATE out-
puts for bus organized system applications The latches ap-
pear transparent to the data when Latch Enable (LE) is
HIGH When LE is low the data satisfying the input timing
requirements is latched Data appears on the bus when the
Output Enable (OE) is LOW When OE is HIGH the bus
output is in the high impedance state The inputs tolerate up
to 7V allowing interface of 5V systems to 3V systems
Features
Y _{Input voltage translation from 5V to 3V}
Y _{Ideal for low power low noise 3 3V applications}
Y _{Available in SOIC JEDEC SOIC EIAJ and TSSOP}
packages
Y _{Guaranteed simultaneous switching noise level and}
dynamic threshold performance
Logic Symbols
IEEE IEC
Connection Diagram
Pin Assignment for
SOIC and TSSOP
TL F 11613–1
Pin Names
D₀ – D₇
LE
OE
O₀ – O₇
TL F 11613 – 4
Description
Data Inputs
Latch Enable Input
Output Enable Input
TRI-STATE Latch Outputs
TL F 11613 – 2
Order Number
See NS Package Number
SOIC JEDEC
74LVX373M
74LVX373MX
M20B
SOIC EIAJ
74LVX373SJ
74LVX373SJX
M20D
TSSOP
74LVX373MTC
74LVX373MTCX
MTC20
TRI-STATE is a registered trademark of National Semiconductor Corporation
C1996 National Semiconductor Corporation TL F 11613
RRD-B30M17 Printed in U S A
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