74LVT16652 Datasheet, PDF (1/6 Pages) National Semiconductor (TI) – Input and output interface capability

ADVANCE INFORMATION
October 1995
74LVT16652
3 3V ABT 16-Bit Transceiver Register
with TRI-STATE Outputs
General Description
The LVT16652 consists of sixteen bus transceiver circuits
with D-type flip-flops and control circuitry arranged for multi-
plexed transmission of data directly from the input bus or
from the internal registers Each byte has separate control
inputs which can be shorted together for full 16-bit opera-
tion Data on the A or B bus will be clocked into the registers
as the appropriate clock pin goes to HIGH logic level Out-
put Enable pins (OEAB OEBA) are provided to control the
transceiver function
The transceivers are designed for low-voltage (3 3V) V_CC
applications but with the capability to provide a TTL inter-
face to a 5V environment The LVT16652 is fabricated with
an advanced BiCMOS technology to achieve high speed
operation similar to 5V ABT while maintaining a low power
dissipation
Features
Y _{Input and output interface capability to systems at 5V}
V_CC
Y _{Bus-Hold data inputs eliminate the need for external}
pull-up resistors to hold unused inputs
Y _{Live insertion extraction permitted}
Y _{Power Up Down high impedance provides glitch-free}
bus loading
Y _{Outputs source sink} b_{32 mA} a_{64 mA}
Y _{Available in SSOP and TSSOP}
Y _{Functionally compatible with the 74 series 16652}
Y _{Latch-up performance exceeds 500 mA}
Connection Diagram
Pin Assignment for
SSOP and TSSOP
Pin Names
A₀ – A₁₆
B₀ – B₁₆
CPAB_n CPBA_n
SAB_n SBA_n
OEAB_n OEBA_n
Description
Data Register A Inputs
TRI-STATE Outputs
Data Register B Inputs
TRI-STATE Outputs
Clock Pulse Inputs
Select Inputs
Output Enable Inputs
Order Number
NS Package
Number
SSOP EIAJ
74LVT16652MEA
74LVT16652MEAX
MS56A
TSSOP JEDEC
74LVT16652MTD
74LVT16652MTDX
MTD56
TRI STATE is a registered trademark of National Semiconductor Corporation
C1996 National Semiconductor Corporation TL F 12024
RRD B30M17 Printed in U S A
TL F 12024 1
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