74LS155 Datasheet, PDF (1/8 Pages) National Semiconductor (TI) – Dual 2-Line to 4-Line Decoders/Demultiplexers

June 1989
54LS155 DM54LS155 DM74LS155
54LS156 DM54LS156 DM74LS156
Dual 2-Line to 4-Line Decoders Demultiplexers
General Description
These TTL circuits feature dual 1-line-to-4-line demultiplex-
ers with individual strobes and common binary-address in-
puts in a single 16-pin package When both sections are
enabled by the strobes the common address inputs se-
quentially select and route associated input data to the ap-
propriate output of each section The individual strobes per-
mit activating or inhibiting each of the 4-bit sections as de-
sired Data applied to input C1 is inverted at its outputs and
data applied at C2 is true through its outputs The inverter
following the C1 data input permits use as a 3-to-8-line de-
coder or 1-to-8-line demultiplexer without external gating
Input clamping diodes are provided on these circuits to mini-
mize transmission-line effects and simplify system design
Features
Y _Applications
Dual 2-to-4-line decoder
Dual 1-to-4-line demultiplexer
3-to-8-line decoder
1-to-8-line demultiplexer
Y _{Individual strobes simplify cascading for decoding or}
demultiplexing larger words
Y _{Input clamping diodes simplify system design}
Y _{Choice of outputs}
Totem-pole (LS155)
Open-collector (LS156)
Y _{Alternate Military Aerospace device (54LS155 156) is}
available Contact a National Semiconductor Sales Of-
fice Distributor for specifications
Connection Diagram and Function Tables
Dual-In-Line Package
Order Number 54LS155DMQB 54LS155FMQB
54LS155LMQB DM54LS155J DM54LS155W
DM74LS155M DM74LS155N 54LS156DMQB
54LS156FMQB DM54LS156J DM54LS156W
DM74LS156M or DM74LS156N
See NS Package Number E20A J16A
M16A N16E or W16A
2-Line-to-4-Line Decoder or
1-Line-to-4-Line Demultiplexer
Inputs
Outputs
Select Strobe Data
B A G1
C1 1Y0 1Y1 1Y2 1Y3
XX
H
LL
L
LH
L
TL F 6395 – 1
HL
L
3-Line-to-8-Line Decoder or
1-Line-to-8-Line Demultiplexer
HH
L
XX
X
X
H
H
H
H
H
L
H
H
H
H
H
L
H
H
H
H
H
L
H
H
H
H
H
L
L
H
H
H
H
Inputs
Outputs
Select
Strobe
Or Data
(0)
(1)
(2)
(3)
(4)
(5)
(6)
(7)
C B A G 2Y0 2Y1 2Y2 2Y3 1Y0 1Y1 1Y2 1Y3
X XX H
L LL L
L LH L
L HL L
L HH L
H LL L
H LH L
H HL L
H HH L
HHHHHHHH
L HHHHHHH
H L HHHHHH
HH L HHHHH
HHH L HHHH
HHHH L HHH
HHHHH L HH
HHHHHH L H
HHHHHHH L
Inputs
Outputs
Select Strobe Data
B A G2
C2 2Y0 2Y1 2Y2 2Y3
XX
H
LL
L
LH
L
HL
L
HH
L
XX
X
X
H
H
H
H
L
L
H
H
H
L
H
L
H
H
L
H
H
L
H
L
H
H
H
L
H
H
H
H
H
C e inputs C1 and C2 connected together
G e inputs G1 and G2 connected together
H e high level L e low level X e don’t care
C1995 National Semiconductor Corporation TL F 6395
RRD-B30M105 Printed in U S A