54LS42 Datasheet, PDF (1/6 Pages) National Semiconductor (TI) – Decimal Decoders

June 1989
54LS42 DM54LS42 DM74LS42 BCD Decimal Decoders
General Description
These BCD-to-decimal decoders consist of eight inverters
and ten four-input NAND gates The inverters are connect-
ed in pairs to make BCD input data available for decoding
by the NAND gates Full decoding of input logic ensures
that all outputs remain off for all invalid (10–15) input condi-
tions
Connection Diagram
Dual-In-Line Package
TL F 6365 – 1
Order Number 54LS42DMQB 54LS42FMQB
DM54LS42J DM54LS42W DM74LS42M or DM74LS42N
See NS Package Number J16A M16A N16E or W16A
Logic Diagram
Features
Y _{Diode clamped inputs}
Y _{Also for applications as 4-line-to-16-line decoders 3-}
line-to-8-line decoders
Y _{All outputs are high for invalid input conditions}
Y _{Alternate Military Aerospace device (54LS42) is avail-}
able Contact a National Semiconductor Sales Office
Distributor for specifications
Function Table
No ^{BCD Inputs}
Decimal Outputs
DCBA0 1 2 3 4 5 6 7 8 9
0 L L L L LHHHHHHHHH
1 L L LHHLHHHHHHHH
2 L LHLHHLHHHHHHH
3 L LHHHHHLHHHHHH
4 LHL LHHHHLHHHHH
5 LHLHHHHHHLHHHH
6 LHHLHHHHHHLHHH
7 LHHHHHHHHHHLHH
8 HL L LHHHHHHHHLH
9 HL LHHHHHHHHHHL
I
N
V
A
L
I
D
H L H L HHHHHHHHHH
H L HHHHHHHHHHHH
HHL LHHHHHHHHHH
HH L HHHHHHHHHHH
HHH L HHHHHHHHHH
HHHHHHHHHHHHHH
H e High Level
L e Low Level
C1995 National Semiconductor Corporation TL F 6365
TL F 6365 – 2
RRD-B30M105 Printed in U S A