54LS192 Datasheet, PDF (1/8 Pages) National Semiconductor (TI) – 54LS192/DM74LS192 Up/Down Decade Counter with Separate Up/Down Clocks

May 1992
54LS192 DM74LS192 Up Down Decade Counter
with Separate Up Down Clocks
General Description
The ’LS192 is an up down BCD decade (8421) counter
Separate Count Up and Count Down Clocks are used and in
either counting mode the circuits operate synchronously
The outputs change state synchronous with the LOW-to-
HIGH transitions on the clock inputs
Separate Terminal Count Up and Terminal Count Down out-
puts are provided which are used as the clocks for a subse-
quent stage without extra logic thus simplifying multistage
counter designs Individual preset inputs allow the circuits to
be used as programmable counters Both the Parallel Load
(PL) and the Master Reset (MR) inputs asynchronously
override the clocks
Connection Diagram
Logic Symbol
Dual-In-Line Package
TL F 10178 – 1
Order Number 54LS192DMQB 54LS192FMQB
54LS192LMQB DM74LS192M or DM74LS192N
See NS Package Number E20A J16A
M16A N16E or W16A
V_CC e Pin 16
GND e Pin 8
TL F 10178 – 2
Pin Names
CP_U
CP_D
MR
PL
P0 – P3
Q0 – Q3
TC_D
TC_U
Description
Count Up Clock Input
(Active Rising Edge)
Count Down Clock Input
(Active Rising Edge)
Asynchronous Master Reset Input
(Active HIGH)
Asynchronous Parallel Load Input
(Active LOW)
Parallel Data Inputs
Flip-Flop Outputs
Terminal Count Down (Borrow)
Output (Active LOW)
Terminal Count Up (Carry)
Output (Active LOW)
Mode Select Table
MR
PL
CP_U
H
X
X
L
L
X
L
H
H
L
H
L
L
H
H
H e HIGH Voltage Level
L e LOW Voltage Level
X e Immaterial
CP_D
X
X
H
H
L
Mode
Reset (Asyn )
Preset (Asyn )
No Change
Count Up
Count Down
C1995 National Semiconductor Corporation TL F 10178
RRD-B30M105 Printed in U S A