54LS160A Datasheet, PDF (1/9 Pages) National Semiconductor (TI) – Synchronous Presettable BCD Decade Counters

May 1992
54LS160A DM74LS160A 54LS162A DM74LS162A
Synchronous Presettable BCD Decade Counters
General Description
The ’LS160 and ’LS162 are high speed synchronous dec-
ade counters operating in the BCD (8421) sequence They
are synchronously presettable for application in programma-
ble dividers and have two types of Count Enable inputs plus
a Terminal Count output for versatility in forming synchro-
nous multistage counters The ’LS160 has an asynchronous
Master Reset input that overrides all other inputs and forces
the outputs LOW The ’LS162 has a Synchronous Reset
input that overrides counting and parallel loading and allows
all outputs to be simultaneously reset on the rising edge of
the clock
Features
Y _{Synchronous counting and loading}
Y _{High speed synchronous expansion}
Y _{Typical count rate of 35 MHz}
Y _{Fully edge triggered}
Connection Diagram
Dual-In-Line Package
Pin
Names
CEP
CET
CP
MR (’160)
SR (’162)
P0 – P3
PE
Q0 – Q3
TC
MR for ’LS160
SR for ’LS162
TL F 10177 – 1
Order Number 54LS160ADMQB 54LS160AFMQB 54LS160ALMQB
54LS162ADMQB 54LS162AFMQB 54LS162ALMQB DM74LS160AM
DM74LS160AN DM74LS162AM or DM74LS162AN
See NS Package Number E20A J16A M16A N16E or W16A
Description
Count Enable Parallel Input
Count Enable Trickle Input
Clock Pulse Input (Active Rising Edge)
Asynchronous Master Reset
Input (Active LOW)
Synchronous Reset
Input (Active LOW)
Parallel Data Inputs
Parallel Enable Input
(Active LOW)
Flip-Flop Outputs
Terminal Count Output
Logic Symbol
V_CC e Pin 16 MR for ’LS160
GND e Pin 8 SR for ’LS162
TL F 10177 – 2
C1995 National Semiconductor Corporation TL F 10177
RRD-B30M105 Printed in U S A