54LS113 Datasheet, PDF (1/6 Pages) National Semiconductor (TI) – Dual JK Edge-Triggered Flip-Flop

54LS113
Dual JK Edge-Triggered Flip-Flop
General Description
The 54LS113 offers individual J K Set and Clock inputs
When the clock goes HIGH the inputs are enabled and data
may be entered The logic level of the J and K inputs may
be changed when the clock pulse is HIGH and the bistable
will perform according to the Truth Table as long as mini-
mum setup and hold times are observed Input data is trans-
ferred to the outputs on the falling edge of the clock pulse
Connection Diagram
Logic Symbol
Dual-In-Line Package
June 1989
TL F 10205 – 1
Order Number 54LS113DMQB
54LS113FMQB or 54LS113LMQB
See NS Package Number E20A J14A or W14B
V_CC e Pin 14
GND e Pin 7
TL F 10205 – 2
Truth Table
Inputs
Output
t_n
J
K
t_n a 1
Q
L
L
Q_n
L
H
L
H
L
H
H
H
Q_n
t_n e Bit Time before Clock Pulse
t_n a 1 e Bit Time after Clock Pulse
H e HIGH Voltage Level
L e LOW Voltage Level
Asynchronous Input
Low input to S_D sets Q to HIGH level
Set is independent of clock
Pin Names
Description
J1 J2 K1 K2
CP1 CP2
SD1 SD2
Q1 Q2 Q1 Q2
Data Inputs
Clock Pulse Inputs (Active Falling Edge)
Direct Set Inputs (Active LOW)
Outputs
C1995 National Semiconductor Corporation TL F 10205
RRD-B30M105 Printed in U S A