54F651SDM Datasheet, PDF (1/10 Pages) National Semiconductor (TI) – Transceivers/Registers

December 1994
54F 74F651  54F 74F652
Transceivers Registers
General Description
These devices consist of bus transceiver circuits with
D-type flip-flops and control circuitry arranged for multi-
plexed transmission of data directly from the input bus or
from internal registers Data on the A or B bus will be
clocked into the registers as the appropriate clock pin goes
to HIGH logic level Output Enable pins (OEAB OEBA) are
provided to control the transceiver function
Features
Y _{Independent registers for A and B buses}
Y _{Multiplexed real-time and stored data}
Y _{Choice of non-inverting and inverting data paths}
’F651 inverting
’F652 non-inverting
Y _{Guaranteed 4000V minimum ESD protection}
Commercial
74F651SPC
74F651SC (Note 1)
74F652SPC
74F652SC (Note 1)
Military
54F651SDM (Note 2)
54F651FM (Note 2)
54F651LM (Note 2)
54F652SDM (Note 2)
54F652FM (Note 2)
54F652LM (Note 2)
Package
Number
N24C
J24F
M24B
W24C
E28A
N24C
J24F
M24B
W24C
E28A
Package Description
24-Lead (0 300 Wide) Molded Dual-In-Line
24-Lead (0 300 Wide) Ceramic Dual-In-Line
24-Lead (0 300 Wide) Molded Small Outline JEDEC
24-Lead Cerpack
24-Lead Ceramic Leadless Chip Carrier Type C
24-Lead (0 300 Wide) Molded Dual-In-Line
24-Lead (0 300 Wide) Ceramic Dual-In-Line
24-Lead (0 300 Wide) Molded Small Outline JEDEC
24-Lead Cerpack
24-Lead Ceramic Leadless Chip Carrier Type C
Note 1 Devices also available in 13 reel Use suffix e SCX
Note 2 Military grade device with environmental and burn-in processing Use suffix e DMQB FMQB and LMQB
Connection Diagrams
Pin Assignment
DIP SOIC and Flatpak
Pin Assignment
for LCC
TL F 9581 – 3
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TL F 9581 – 4
RRD-B30M75 Printed in U S A