54F64DM Datasheet, PDF (1/6 Pages) National Semiconductor (TI) – 4-2-3-2-Input AND-OR-Invert Gate

November 1994
54F 74F64
4-2-3-2-Input AND-OR-Invert Gate
General Description
This device contains gates configured to perform a 4-2-3-2
input AND-OR-INVERT function
Commercial
74F64PC
74F64SC (Note 1)
Military
54F64DM (Note 2)
54F64FM (Note 2)
54F64LM (Note 2)
Package
Number
N14A
J14A
M14A
W14B
E20A
Package Description
14-Lead (0 300 Wide) Molded Dual-In-Line
14-Lead Ceramic Dual-In-Line
14-Lead (0 150 Wide) Molded Small Outline JEDEC
14-Lead Cerpack
20-Lead Ceramic Leadless Chip Carrier Type C
Note 1 Devices also available in 13 reel Use suffix e SCX
Note 2 Military grade device with environmental and burn-in processing Use suffix e DMQB FMQB and LMQB
Logic Symbol
Connection Diagrams
IEEE IEC
Pin Assignment for
DIP SOIC and Flatpak
Pin Assignment
for LCC
TL F 9467 – 2
TL F 9467–3
Unit Loading Fan Out
Pin Names
A_n B_n C_n D_n
O
Description
Inputs
Output
54F 74F
UL
HIGH LOW
10 10
50 33 3
Input I_IH I_IL
Output I_OH I_OL
20 mA b0 6 mA
b1 mA 20 mA
TRI-STATE is a registered trademark of National Semiconductor Corporation
C1995 National Semiconductor Corporation TL F 9467
TL F 9467 – 1
RRD-B30M105 Printed in U S A