54F410DM Datasheet, PDF (1/8 Pages) National Semiconductor (TI) – Register StackÐ16 x 4 RAM TRI-STATEE Output Register

August 1995
54F 74F410 Register Stack 16 x 4 RAM
TRI-STATE Output Register
General Description
The ’F410 is a register-oriented high-speed 64-bit Read
Write Memory organized as 16-words by 4-bits An edge-
triggered 4-bit output register allows new input data to be
written while previous data is held TRI-STATE outputs are
provided for maximum versatility The ’F410 is fully compati-
ble with all TTL families
Features
Y _{Edge-triggered output register}
Y _{Typical access time of 35 ns}
Y _{TRI-STATE outputs}
Y _{Optimized for register stack operation}
Y _{18-pin package}
Y _{9410 replacement}
Commercial
Military
Package
Number
Package Description
74F410PC
N18A
18-Lead (0 300 Wide) Molded Dual-In-Line
54F410DM (Note 1)
J18A
18-Lead Ceramic Dual-In-Line
74F410SC
M20B
20-Lead (0 300 Wide) Molded Small Outline JEDEC
54F410LM
W20A
20-Lead Cerpak
Note 1 Military grade device with environmental and burn-in processing Use suffix e DMQB LMQB
Logic Symbol
Connection Diagrams
Pin Assignment
for DIP and SOIC
Pin Assignment
for LCC
TL F 9538–3
TL F 9538 – 1
TL F 9538 – 2
TRI-STATE is a registered trademark of National Semiconductor Corporation
C1995 National Semiconductor Corporation TL F 9538
RRD-B30M105 Printed in U S A