54F407 Datasheet, PDF (1/10 Pages) National Semiconductor (TI) – DATA ACCESS REGISTER

December 1994
54F407
Data Access Register
General Description
The ’F407 Data Access Register (DAR) performs memory
address arithmetic for RAM resident stack applications It
contains three 4-bit registers intended for Program Counter
(R₀) Stack Pointer (R₁) and Operand Address (R₂) The
’F407 implements 16 instructions which allow either pre- or
post-decrement increment and register-to-register transfer
in a single clock cycle It is expandable in 4-bit increments
and can operate at a 30 MHz microinstruction rate on a
16-bit word The TRI-STATE outputs are provided for bus-
oriented applications The ’F407 is fully compatible with all
TTL families
Features
Y _{High-speed greater than a 30 MHz microinstruction}
rate
Y _{Three 4-bit registers}
Y _{16 instructions for register manipulation}
Y _{Two separate output ports one transparent}
Y _{Relative addressing capability}
Y _{TRI-STATE Outputs}
Y _{Optional pre- or post- arithmetic}
Y _{Expandable in multiples of four bits}
Y _{24-pin slim package}
Y _{9407 replacement}
Military
54F407DM (Note 1)
54F407SDM (Note 1)
54F407FM (Note 1)
54F407FM (Note 1)
Package
Number
J24A
J24F
W24C
E28A
Package Description
24-Lead Ceramic Dual-In-Line
24-Lead (0 300 Wide) Ceramic Dual-In-Line
24-Lead Cerpack
28-Lead Ceramic Leadless Chip Carrier Type C
Note 1 Military grade device with environmental and burn-in processing Use suffix e DMQB FMQB and LMQB
Logic Symbol
Connection Diagrams
Pin Assignment
for DIP and Flatpak
Pin Assignment
for LCC
TL F 9537–3
TL F 9537 – 1
TL F 9537 – 2
TRI-STATE is a registered trademark of National Semiconductor Corporation
C1995 National Semiconductor Corporation TL F 9537
RRD-B30M105 Printed in U S A