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| 54F32 Datasheet, PDF (1/6 Pages) National Semiconductor (TI) – Quad 2-Input OR Gate | |||
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December 1994
54F 74F32
Quad 2-Input OR Gate
General Description
This device contains four independent gates each of which
performs the logic OR function
Features
Y Guaranteed 4000V minimum ESD protection
Commercial
74F32PC
74F32SC (Note 1)
74F32SJ (Note 1)
Military
54F32DM (Note 2)
54F32FM (Note 2)
54F32LM (Note 2)
Package
Number
N14A
J14A
M14A
M14D
W14B
E20A
Package Description
14-Lead (0 300 Wide) Molded Dual-In-Line
14-Lead Ceramic Dual-In-Line
14-Lead (0 150 Wide) Molded Small Outline JEDEC
14-Lead (0 300 Wide) Molded Small Outline EIAJ
14-Lead Cerpack
20-Lead Ceramic Leadless Chip Carrier Type C
Note 1 Devices also available in 13 reel Use suffix e SCX and SJX
Note 2 Military grade device with environmental and burn-in processing Use suffix e DMQB FMQB and LMQB
Logic Symbol
Connection Diagrams
IEEE IEC
Pin Assignment for
DIP SOIC and Flatpak
Pin Assignment
for LCC
TL F 9463â3
TL F 9463 â 2
Unit Loading Fan Out
Pin Names
An Bn
On
Description
Inputs
Outputs
54F 74F
UL
HIGH LOW
10 10
50 33 3
Input IIH IIL
Output IOH IOL
20 mA b0 6 mA
b1 mA 20 mA
TRI-STATE is a registered trademark of National Semiconductor Corporation
C1995 National Semiconductor Corporation TL F 9463
TL F 9463 â 1
RRD-B30M75 Printed in U S A
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