54F273DM Datasheet, PDF (1/8 Pages) National Semiconductor (TI) – Octal D Flip-Flop

May 1995
54F 74F273
Octal D Flip-Flop
General Description
The ’F273 has eight edge-triggered D-type flip-flops with in-
dividual D inputs and Q outputs The common buffered
Clock (CP) and Master Reset (MR) inputs load and reset
(clear) all flip-flops simultaneously
The register is fully edge-triggered The state of each D in-
put one setup time before the LOW-to-HIGH clock tran-
sition is transferred to the corresponding flip-flop’s Q out-
put
All outputs will be forced LOW independently of Clock or
Data inputs by a LOW voltage level on the MR input The
device is useful for applications where the true output only is
required and the Clock and Master Reset are common to all
storage elements
Features
Y _{Ideal buffer for MOS microprocessor or memory}
Y _{Eight edge-triggered D flip-flops}
Y _{Buffered common clock}
Y _{Buffered asynchronous Master Reset}
Y _{See ’F377 for clock enable version}
Y _{See ’F373 for transparent latch version}
Y _{See ’F374 for TRI-STATE version}
Y _{Guaranteed 4000V minimum ESD protection}
Commercial
74F273PC
74F273SC (Note 1)
74F273SJ (Note 1)
Military
54F273DM (Note 2)
54F273FM (Note 2)
54F273LM (Note 2)
Package
Number
N20A
J20A
M20B
M20D
W20A
E20A
Package Description
20-Lead (0 300 Wide) Molded Dual-In-Line
20-Lead Ceramic Dual-In-Line
20-Lead (0 300 Wide) Molded Small Outline JEDEC
20-Lead (0 300 Wide) Molded Small Outline EIAJ
20-Lead Cerpack
20-Lead Ceramic Leadless Chip Carrier Type C
Note 1 Devices also available in 13 reel Use suffix e SCX and SJX
Note 2 Military grade device with environmental and burn-in processing Use suffix e DMQB FMQB and LMQB
Logic Symbols
IEEE IEC
TL F 9511 – 3
TRI-STATE is a registered trademark of National Semiconductor Corporation
C1995 National Semiconductor Corporation TL F 9511
TL F 9511 – 5
RRD-B30M75 Printed in U S A