54F219DL Datasheet, PDF (1/8 Pages) National Semiconductor (TI) – 64-Bit Random Access Memory with TRI-STATEE Outputs

November 1994
54F 74F219
64-Bit Random Access Memory with TRI-STATE
Outputs
General Description
The ’F219 is a high-speed 64-bit RAM organized as a
16-word by 4-bit array Address inputs are buffered to mini-
mize loading and are fully decoded on-chip The outputs are
TRI-STATE and are in the high-impedance state whenever
the Chip Select (CS) input is HIGH The outputs are active
only in the Read mode This device is similar to the ’F189
but features non-inverting rather than inverting data out-
puts
Features
Y _{TRI-STATE outputs for data bus applications}
Y _{Buffered inputs minimize loading}
Y _{Address decoding on-chip}
Y _{Diode clamped inputs minimize ringing}
Y _{Available in SOIC (300 mil only)}
Commercial
74F219PC
74F219SC (Note 1)
74F219SJ (Note 1)
Military
54F219DL (Note 2)
54F219FL (Note 2)
54F219LL (Note 2)
Package
Number
N16E
J16A
M16B
M16D
W16A
E20A
Package Description
16-Lead (0 300 Wide) Molded Dual-In-Line
16-Lead Ceramic Dual-In-Line
16-Lead (0 300 Wide) Molded Small Outline JEDEC
16-Lead (0 300 Wide) Molded Small Outline EIAJ
16-Lead Cerpack
20-Lead Ceramic Leadless Chip Carrier Type C
Note 1 Devices also available in 13 reel Use suffix e SCX and SJX
Note 2 Military grade device with environmental and burn-in processing Use suffix e DLQB FLQB and LLQB
Logic Symbol
Connection Diagrams
Pin Assignment for
DIP SOIC and Flatpak
Pin Assignment
for LCC
TL F 9500–1
TL F 9500 – 2
TRI-STATE is a registered trademark of National Semiconductor Corporation
C1995 National Semiconductor Corporation TL F 9500
TL F 9500 – 3
RRD-B30M105 Printed in U S A