54ACTQ377 Datasheet, PDF (1/6 Pages) National Semiconductor (TI) – Octal D Flip-Flop with Clock Enable

September 1998
54ACTQ377
Octal D Flip-Flop with Clock Enable
General Description
The ACTQ377 has eight edge-triggered, D-type flip-flops
with individual D inputs and Q outputs. The common buff-
ered Clock (CP) input loads all flip-flops simultaneously,
when the Clock Enable (CE) is LOW.
The register is fully edge-triggered. The state of each D in-
put, one setup time before the LOW-to-HIGH clock transi-
tion, is transferred to the corresponding flip-flop’s Q output.
The CE input must be stable only one setup time prior to the
LOW-to-HIGH clock transition for predictable operation.
The ACTQ377 utilizes FACT Quiet Series^® technology to
guarantee quiet output switching and improved dynamic
threshold performance. FACT Quiet Series features GTO^®
output control and undershoot corrector in addition to a split
ground bus for superior performance.
Features
n Ideal for addressable register applications
n Clock enable for address and data synchronization
applications
n Eight edge-triggered D flip-flops
n Buffered common clock
n Outputs source/sink 24 mA
n See ’273 for master reset version
n See ’373 for transparent latch version
n See ’374 for TRI-STATE^® version
n Guaranteed simultaneous switching noise level and
dynamic threshold performance
n TTL-compatible inputs and outputs
n Standard Microcircuit Drawing (SMD) 5962-9219001
Logic Symbols
IEEE/IEC
DS100357-1
Pin
Names
D₀– D₇
CE
Q₀– Q₇
CP
Description
Data Inputs
Clock Enable (Active LOW)
Data Outputs
Clock Pulse Input
DS100357-2
GTO^® is a trademark of National Semiconductor Corporation.
TRI-STATE^® is a registered trademark of National Semiconductor Corporation.
FACT^® and FACT Quiet Series^® are registered trademarks of Fairchild Semiconductor Corporation.
© 1998 National Semiconductor Corporation DS100357
www.national.com