54ACTQ273 Datasheet, PDF (1/8 Pages) National Semiconductor (TI) – Quiet Series Octal D Flip-Flop

August 1998
54ACTQ273
Quiet Series Octal D Flip-Flop
General Description
The ACTQ273 has eight edge-triggered D-type flip-flops with
individual D inputs and Q outputs. The common buffered
Clock (CP) and Master Reset (MR) input load and reset
(clear) all flip-flops simultaneously.
The register is fully edge-triggered. The state of each D in-
put, one setup time before the LOW-to-HIGH clock transi-
tion, is transferred to the corresponding flip-flop’s Q output.
All outputs will be forced LOW independently of Clock or
Data inputs by a LOW voltage level on the MR input. The de-
vice is useful for applications where the true output only is re-
quired and the Clock and Master Reset are common to all
storage elements.
The ACTQ utilizes NSC Quiet Series technology to guaran-
tee quiet output switching and improved dynamic threshold
performance. FACT Quiet Series™ features GTO™ output
control and undershoot corrector in addition to a split ground
bus for superior performance.
Features
n I_CC reduced by 50%
n Guaranteed simultaneous switching noise level and
dynamic threshold performance
n Improved latch-up immunity
n Buffered common clock and asynchronous master reset
n Outputs source/sink 24 mA
n Faster prop delays than the standard ’AC/’ACT273
n 4 kV minimum ESD immunity
n Standard Microcircuit Drawing (SMD)
5962-89735
Logic Symbols
IEEE/IEC
DS100240-1
Pin Names
D₀– D₇
MR
CP
Q₀– Q₇
Description
Data Inputs
Master Reset
Clock Pulse Input
Data Outputs
DS100240-2
GTO™ is a trademark of National Semiconductor Corporation.
FACT^® is a registered trademark of Fairchild Semiconductor Corporation.
FACT Quiet Series™ is a trademark of Fairchild Semiconductor Corporation.
© 1998 National Semiconductor Corporation DS100240
www.national.com