54ACT899 Datasheet, PDF (1/12 Pages) National Semiconductor (TI) – 9-Bit Latchable Transceiver with Parity Generator/Checker

August 1998
54ACT899
9-Bit Latchable Transceiver with Parity
Generator/Checker
General Description
The ACT899 is a 9-bit to 9-bit parity transceiver with trans-
parent latches. The device can operate as a feed-through
transceiver or it can generate/check parity from the 8-bit data
busses in either direction. The ACT899 features independent
latch enables for the A-to-B direction and the B-to-A direc-
tion, a select pin for ODD/EVEN parity, and separate error
signal output pins for checking parity.
Features
n Latchable transceiver with output sink of 24 mA
n Option to select generate parity and check or
“feed-through” data/parity in directions A-to-B or B-to-A
n Independent latch enable for A-to-B and B-to-A
directions
n Select pin for ODD/EVEN parity
n ERRA and ERRB output pins for parity checking
n Ability to simultaneously generate and check parity
n May be used in system applications in place of the ’280
n May be used in system applications in place of the ’657
and ’373 (no need to change T/R to check parity)
n 4 kV minimum ESD immunity
n Standard Microcircuit Drawing (SMD) 5962-9314101
Logic Symbol
Connection Diagram
DS100245-1
Pin Assignment for LCC
Pin Names
A₀– A₇
B₀– B₇
APAR, BPAR
ODD/EVEN
GBA, GAB
SEL
LEA, LEB
ERRA, ERRB
Description
A Bus Data Inputs/Data Outputs
B Bus Data Inputs/Data Outputs
A and B Bus Parity Inputs
ODD/EVEN Parity Select, Active LOW
for EVEN Parity
Output Enables for A or B Bus, Active
LOW
Select Pin for Feed-Through or
Generate Mode, LOW for Generate
Mode
Latch Enables for A and B Latches,
HIGH for Transparent Mode
Error Signals for Checking Generated
Parity with Parity In, LOW if Error
Occurs
DS100245-2
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© 1998 National Semiconductor Corporation DS100245
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